AT89LP52-20AU Atmel, AT89LP52-20AU Datasheet - Page 98

• Manufacturer Part Number: AT89LP52-20AU
• Description: IC MCU 8051 8K FLASH SPI 44TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP52-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: Serial
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

18.6
The values shown in this table are valid for T
ating conditions, load capacitance for Port 0, ALE and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.
Parameters refer to
Table 18-4.
Notes:
98
Symbol
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LHLL
AVLL
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
PXAV
AVIV
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
QVWH
WHQX
RLAZ
WHAX
WHLH
CLCL
External Memory Characteristics
1. Compatibility Mode timing for MOVX also applies to Fast Mode during exeternal execution of MOVX.
2. This assumes 50% clock duty cycle. The half period depends on the clock high value t
3. This assumes 50% clock duty cycle. The half period depends on the clock low value t
4. In some cases parameter t
5. The strobe pulse width may be lengthened by 1, 2 or 3 additional t
AT89LP51/52 - Preliminary
Parameter
Oscillator Frequency
ALE Pulse Width
Address Valid to ALE Low
Address Hold after ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse WIdth
PSEN Low to Valid Instruction In
Input Instruction Hold after PSEN
Input Instruction Float after PSEN
PSEN to Address Valid
Address to Valid Instruction In
PSEN Low to Address Float
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
Data Hold after RD
Data Float after RD
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address to RD or WR Low
Data Valid to WR Transition
Data Valid to WR High
Data Hold after WR
RD Low to Address Float
Address Hold after RD or WR High
RD or WR High to ALE High
External Program and Data Memory Characteristics
Figure
(5)
(5)
18-6,
Figure 18-7
LHLL
may have a minimum of 0.5t
A
and
= -40°C to 85°C and V
Figure
0.5t
0.5t
0.5t
1.5t
0.5t
1.5t
2t
1t
4t
1t
1t
0.5t
18-8.
3t
3t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
Compatibility Mode
Min
CLCL
CLCL
0
0
0
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
(2)
(2)
(2)
(3)
(3)
(2)
(3)
(2)
(2)
(2)
CLCL
DD
during Fast mode external execution with DISALE = 0.
1.5t
0.5t
2.5t
4.5t
-1t
1.5t
0.5t
CLCL
2.5t
2t
4t
= 2.4 to 5.5V, unless otherwise noted. Under oper-
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
Max
CLCL
CLCL
CLCL
24
10
using wait states.
(1)
+ d
- d
- d
- d
- d
- d
- d
- d
+ d
+ d
- d
(2)
(2)
(2)
(2)
(2)
0.5t
0.5t
0.5t
1.5t
0.5t
1.5t
0.5t
1.5t
0.5t
0.5t
t
CLCL
t
t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCX
Min
CHCX
0
0
0
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
- d
Fast Mode
(low duty cycle).
(4)
(high duty cycle).
(2)
(3)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
-0.5t
1.5t
0.5t
2.5t
2.5t
(1)
2t
2t
t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
Max
24
10
+ d
- d
- d
- d
- d
- d
- d
- d
- d
+ d
3709B–MICRO–12/10
(2)
(2)
(2)
(2)
(2)
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns