ST16C554DCQ-0A-EB Exar Corporation, ST16C554DCQ-0A-EB Datasheet - Page 18

• Manufacturer Part Number: ST16C554DCQ-0A-EB
• Description: EVAL BOARD FOR ST16C554D 64TQFP
• Manufacturer: Exar Corporation

Specifications of ST16C554DCQ-0A-EB

• Interface Type: UART
• Data Bus Width: 8 bit
• For Use With/related Products: ST16C554D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST16C554/554D
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
associated with each of these interrupt levels.
•
•
•
•
•
•
•
•
•
•
]
ISR[0]: Interrupt Status
•
•
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
ISR[5:4]: Reserved (Default 0)
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.4
4.4.1
4.4.2
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by THR empty (non-FIFO mode) or TX FIFO empty (FIFO mode).
MSR is by any of the MSR bits 0, 1, 2 and 3.
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or by writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
Interrupt Status Register (ISR)
P
Interrupt Generation:
Interrupt Clearing:
L
RIORITY
EVEL
1
2
3
4
5
-
Table
B
9, shows the data values (bit 0-3) for the interrupt priority levels and the interrupt sources
IT
0
1
0
0
0
0
-3
ISR R
B
EGISTER
IT
T
1
1
1
0
0
0
ABLE
-2
9: I
S
B
TATUS
IT
1
0
0
1
0
0
NTERRUPT
-1
B
ITS
B
IT
0
0
0
0
0
1
-0
S
OURCE AND
18
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Empty)
MSR (Modem Status Register)
None (default)
P
RIORITY
S
OURCE OF INTERRUPT
L
EVEL
REV. 4.0.1
Table
9).