ST16C554DCQ-0A-EB Exar Corporation, ST16C554DCQ-0A-EB Datasheet - Page 12

• Manufacturer Part Number: ST16C554DCQ-0A-EB
• Description: EVAL BOARD FOR ST16C554D 64TQFP
• Manufacturer: Exar Corporation

Specifications of ST16C554DCQ-0A-EB

• Interface Type: UART
• Data Bus Width: 8 bit
• For Use With/related Products: ST16C554D
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST16C554/554D
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still LOW it is validated. Evaluating the
start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and
stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s),
they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive
FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in
RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it
reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready
time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is
equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0. See
F
F
2.10
2.9.2
2.9.3
IGURE
IGURE
6. T
7. T
Receiver
Transmitter Operation in non-FIFO Mode
Transmitter Operation in FIFO Mode
RANSMITTER
RANSMITTER
O
O
16X Clock
PERATION IN NON
16X Clock
PERATION IN
Data
Byte
Data Byte
Transmit
Transmit Shift Register (TSR)
FIFO M
Transmit Data Shift Register
-FIFO M
Transmit
Register
Holding
(THR)
ODE
Transmit
( TSR )
FIFO
ODE
12
becomes empty. FIFO is
enabled by FCR bit-0 =1.
THR Interrupt (ISR bit-1)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
when the TX FIFO
M
S
B
L
S
B
TXNOFIFO1
TXFIFO1
Figure 8
and
Figure
REV. 4.0.1
9.