XR18W750/753-0B-EB Exar Corporation, XR18W750/753-0B-EB Datasheet - Page 27

• Manufacturer Part Number: XR18W750/753-0B-EB
• Description: EVAL BOARD FOR XR18W750/753
• Manufacturer: Exar Corporation

Specifications of XR18W750/753-0B-EB

• Silicon Manufacturer: Exar
• Silicon Core Number: XR18W750
• Kit Application Type: Communication & Networking
• Application Sub Type: Wireless UART Controller
• Kit Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.0
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
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MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
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MCR[2]: Reserved
OP1# is not available as an output pin on the enhanced UART. But it is available for use during Internal
Loopback Mode. In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: OP2# Output / INT Output Enable
This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output. Also, if 16/68# pin selects Motorola bus interface mode, this bit must be set to
logic 0.
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MCR[4]: Internal Loopback Enable
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MCR[7:5]: Reserved
For normal operation, these register bits should be ’0’.
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
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LSR[1]: Receiver Overrun Error Flag
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LSR[2]: Receive Data Parity Error Tag
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LSR[3]: Receive Data Framing Error Tag
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5.8
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
Logic 0 = Force RTS# HIGH (default).
Logic 1 = Force RTS# LOW.
Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).
Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Logic 0 = No data in receive holding register or FIFO (default).
Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
Line Status Register (LSR) - Read Only
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Figure
WIRELESS UART CONTROLLER
10.
XR18W750