XR18W750/753-0B-EB Exar Corporation, XR18W750/753-0B-EB Datasheet - Page 13

• Manufacturer Part Number: XR18W750/753-0B-EB
• Description: EVAL BOARD FOR XR18W750/753
• Manufacturer: Exar Corporation

Specifications of XR18W750/753-0B-EB

• Silicon Manufacturer: Exar
• Silicon Core Number: XR18W750
• Kit Application Type: Communication & Networking
• Application Sub Type: Wireless UART Controller
• Kit Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.0
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
F
F
3.9.2
3.9.3
IGURE
IGURE
5. T
6. T
Transmitter Operation in non-FIFO Mode
Transmitter Operation in FIFO Mode
RANSMITTER
RANSMITTER
Auto CTS Flow Control (CTS# pin)
16X Clock
16X Clock
O
O
Data
Byte
PERATION IN NON
PERATION IN
Data Byte
Transmit
Transmit Shift Register (TSR)
FIFO
Transmit
Register
-FIFO M
Holding
(THR)
Transmit Data Shift Register
AND
F
LOW
Transmit
ODE
FIFO
(TSR)
13
C
ONTROL
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
ODE
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
bit-0=1
empty. FIFO is enabled by FCR
M
S
B
WIRELESS UART CONTROLLER
L
S
B
TXNOFIFO1
XR18W750