XRD8799AIQ Exar Corporation, XRD8799AIQ Datasheet - Page 9

• Manufacturer Part Number: XRD8799AIQ
• Description: IC ADC 10BIT 2MSPS 44PQFP
• Manufacturer: Exar Corporation

Specifications of XRD8799AIQ

• Number Of Bits: 10
• Sampling Rate (per Second): 2M
• Data Interface: Parallel
• Number Of Converters: 8
• Power Dissipation (max): 450mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XRD8799
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.00
F
THEORY OF OPERATION
The XRD8799 converts analog voltages into 1024
digital codes by encoding the outputs of coarse and
fine comparators. Digital logic is used to generate the
overflow bit. The conversion is synchronous with the
clock and it is accomplished in 2 clock periods.
The reference resistance ladder is a series of resis-
tors. The fine comparators use a patented interpola-
tion circuit to generate the equivalent of 1024 evenly
spaced reference voltages between V
V
The clock signal generates the two internal phases,
ure 1). The rising edge of the CLK input marks the
end of the sampling phase ( S). Internal delay of the
clock circuitry will delay the actual instant when S
1.0 ANALOG-TO-DIGITAL CONVERSION
B (CLK high) and S (CLK low = sample) (See Fig-
IGURE
REF(+)
CLOCK
Analog
.
3. XRD8799 T
Sample
Input
Data
N-1
Balance
Auto
IMING
Sample
V
V
OH
OL
t
S
N
D
t
R
IAGRAM
Balance
Auto
T
t
S
AP
t
B
REF(-)
t
HLD
t
DL
t
F
Sample
N-1
N+1
and
V
V
IH
IL
9
disconnects the latches from the comparators. This
delay is called aperture delay (t
The coarse comparators make the first pass conver-
sion and selects a ladder range for the fine compara-
tors. The fine comparators are connected to the se-
lected range during the next B phase.
F
A
Timing
Figure 3 shows this relationship as a timing chart. A
sampling, ladder sampling and output data relation-
ships are shown for the general case where the levels
which drive the ladder need to change for each sam-
pled A
last A
time. If the ladder's levels change by more than 1
LSB, one of the samples must be discarded. Also
note that the clock low period for the discarded A
can be reduced to the minimum t
IGURE
Ref
Ladder
Selected
Range
IN
VIN
VIN
Sampling, Ladder Sampling, and Conversion
IN
IN
4. XRD8799 C
VTAP
VTAP
sample and next A
time point. The ladder is referenced for both
B
S
S
B
OMPARATORS
COARSE COMPARATOR
FINE COMPARATOR
IN
sample at the same
B
S
AP
S
).
time.
xr
xr
S
B
Latch
Latch
IN
IN