XRD8799AIQ Exar Corporation, XRD8799AIQ Datasheet - Page 14

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XRD8799AIQ

Manufacturer Part Number
XRD8799AIQ
Description
IC ADC 10BIT 2MSPS 44PQFP
Manufacturer
Exar Corporation
Datasheet

Specifications of XRD8799AIQ

Number Of Bits
10
Sampling Rate (per Second)
2M
Data Interface
Parallel
Number Of Converters
8
Power Dissipation (max)
450mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-BQFP
Lead Free Status / RoHS Status
Contains lead / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XRD8799AIQ
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XRD8799AIQ-F
Manufacturer:
SEIKO
Quantity:
12 400
xr
xr
F
The following information will be useful in maximizing
the performance of the XRD8799.
1. All signals should not exceed AV
2. Any input pin which can see a value outside the
3. The design of a PC board will affect the accuracy
4. The analog input signal (V
5. The analog input should be driven by a low
6. Analog and digital ground planes should be sub-
2.0 APPLICATION NOTES
IGURE
AGND -0.5 V or DV
absolute maximum ratings (AV
or AGND -0.5 V) should be protected by diode
clamps (HP5082-2835) from input pin to the sup-
plies. All XRD8799 inputs have input protection
diodes which will protect the device from short
transients outside the supply ranges.
of XRD8799. Use of wire wrap is not recom-
mended.
and should be properly routed and terminated. It
should be shielded from the clock and digital out-
puts so as to minimize cross coupling and noise
pickup.
impedance (less than 50 ).
stantial and common at one point only. The
16. T
YPICAL
C
IRCUIT
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
DD
+0.5 V or DGND -0.5 V.
C1 = 4.7 or 10 F Tantalum
C2 = 0.1 F Chip Cap or low inductance cap
R
T
Reference
= Clock Transmission Line Termination
C
Voltage
Source
IN
ONNECTIONS
) is quite sensitive
DD
+
-
DD
or DV
+0.5 V or
1 of 8
C1
A
DD
IN
C2
+0.5 V
C1
Buffer
50 to 100
Isolation of
Resistive
C2
Z < 100
14
C1
10. The digital output should not drive long wires.
7. DV
8. DV
9. Each power supply and reference voltage pin
C2
ground plane should act as a shield for parasitics
and not a return path for signals. To reduce noise
levels, use separate low impedance ground
paths. DGND should not be shared with other
digital circuitry. If separate low impedance paths
cannot be provided, DGND should be connected
to AGND next to the XRD8799.
cuitry to avoid conversion errors caused by digital
supply transients. DV
be connected to AV
XRD8799. DGND and AGND are connected
internally.
should be decoupled with a ceramic (0.1 F) and
a tantalum (10 F) capacitor as close to the
device as possible.
The capacitive coupling and reflection will con-
tribute noise to the conversion. When driving dis-
tant loads, buffers should be used. 100
tors in series with the digital outputs in some
applications reduces the digital output disruption
of A
C1A, C2A
DD
DD
IN
AV
AIN1
AIN8
.
should not be shared with other digital cir-
and AV
DD
+5 V
V
3/4 R
1/4 R
V
V
AGND
(Substrate)
REF(+)
REF(-)
REF1(-)
XRD8799
DD
DGND
are connected inside the
CLK
DD
C1D, C2D
DV
DD
R
DD
T
next to the XRD8799.
for the XRD8799 should
WR
CLK
A2
A1
A0
OE
OFW
DB9 - DB0
XRD8799
REV. 1.00
resis-

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