XRD8799AIQ Exar Corporation, XRD8799AIQ Datasheet - Page 11

• Manufacturer Part Number: XRD8799AIQ
• Description: IC ADC 10BIT 2MSPS 44PQFP
• Manufacturer: Exar Corporation

Specifications of XRD8799AIQ

• Number Of Bits: 10
• Sampling Rate (per Second): 2M
• Data Interface: Parallel
• Number Of Converters: 8
• Power Dissipation (max): 450mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XRD8799
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.00
F
T
The formulas for Differential Non-Linearity (DNL), In-
tegral Non-Linearity (
rors (EZS, EFS) are:
F
ESTER
IGURE
IGURE
DNL (001) = V002 - V001 - LSB
: : :
DNL (3FE) = V3FF - V3FE - LSB
EFS (full scale error) = V3FF - [V
EZS (zero scale error) = V001 - [V
DIGITAL
CODES
V
000
REF(-)
0.5
Analog
Input
Output
Codes
7. DNL M
8. R
LSB
V001
(N) Code Width = V
LSB = [ V
DNL
EZS
EAL
(N)
001
= [ V
A/D T
REF(+)
V002
EASUREMENT
DNL
(N+1)
002
IN
- V
- V
RANSFER
L) and zero and full scale er-
REF(-)
(N)
(N+1)
LSB
] - LSB
] / 1024
- V
(N)
O
C
V
N
URVE
3FE
REF(-)
P
REF(+)
3FE
RODUCTION
EFS
+ 0.5 * LSB]
1.5 LSB
-1.5 * LSB]
V
V
V
N + 1
N
N - 1
3FF
(N+1)
(N)
3FF
V
REF(+)
V
11
Figure 8 shows the zero scale and full scale error
terms.
Figure 9 gives a visual definition of the INL error. The
chart shows a 3-bit converter transfer curve with
greatly exaggerated DNL errors to show the deviation
of the real transfer curve from the ideal one.
After a tester has measured all the transition voltag-
es, the computer draws a line parallel to the ideal
transfer line. By definition the best fit line makes
equal the positive and the negative INL errors. For ex-
ample, an INL error of -1 to +2 LSB's relative to the
Ideal Line would be +1.5 LSB's relative to the best fit
line.
F
A system will clock the XRD8799 continuously or it
will give clock pulses intermittently when a conversion
is desired. The timing of Figure 10a shows normal
operation, while the timing of Figure 10b keeps the
XRD8799 in balance and ready to sample the analog
input.
1.2 C
IGURE
7
6
5
4
3
2
1
9. INL E
LOCK AND
EZS
Output
Codes
INL
RROR
C
Real Transfer Line
ONVERSION
LSB
C
ALCULATION
T
IMING
Analog Input (Volt)
Ideal Transfer Line
xr
xr
Best Fit Line
EFS