XR17V352IB113-F Exar Corporation, XR17V352IB113-F Datasheet - Page 52
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XR17V352IB113-F
Manufacturer Part Number
XR17V352IB113-F
Description
IC UART PCIE 256B DUAL 113FPBGA
Manufacturer
Exar Corporation
Datasheet
1.XR17V352IB113-F.pdf
(64 pages)
Specifications of XR17V352IB113-F
Number Of Channels
2, DUART
Package / Case
113-LFBGA
Features
*
Fifo's
256 Byte
Protocol
RS485
Voltage - Supply
3.3V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
25 Mbps
Supply Current
120 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
No. Of Channels
2
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
BGA
No. Of Pins
113
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR17V352IB113-F
Manufacturer:
EXAR
Quantity:
3 500
Company:
Part Number:
XR17V352IB113-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR17V352IB113-F
Manufacturer:
EXAR/艾科嘉
Quantity:
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XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
MCR[2]: DTR# or RTS# for Auto Flow Control (OP1 in Local Loopback Mode)
DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by
EFR bit [6]. DTR# selection is associated with DSR# and RTS# is with CTS#.
•
•
In Local Loopback mode (MCR[4] = 1), this bit acts as the legacy OP1 output and controls the RI bit in the MSR
register, as shown in
MCR[1]: RTS# Output
The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit [6] and MCR bit [2]=0. If
the modem interface is not used, this output may be used for general purpose.
•
•
MCR[0]: DTR# Output
The DTR# pin may be used for automatic hardware flow control enabled by EFR bit [6] and MCR bit [2]=1. If
the modem interface is not used, this output may be used for general purpose.
•
•
This register provides the status of data transfers between the UART and the host. If IER bit [2] is set to a
logic 1, an LSR interrupt will be generated immediately when any character in the RX FIFO has an error (parity,
framing, overrun, break).
LSR[7]: Receive FIFO Data Error Flag
•
•
LSR[6]: Transmitter Empty Flag
This bit is the Transmitter Empty indicator. This bit is set to a logic 1 whenever both the transmit FIFO (or THR,
in non-FIFO mode) and the transmit shift register (TSR) are both empty. It is set to logic 0 whenever either the
TX FIFO or TSR contains a data character.
LSR[5]: Transmit FIFO Empty Flag
This bit is the Transmit FIFO Empty indicator. This bit indicates that the transmitter is ready to accept a new
character for transmission. This bit is set to a logic HIGH when the last data byte is transferred from the
transmit FIFO to the transmit shift register. The bit is reset to logic 0 as soon as a data byte is loaded into the
transmit FIFO. In the non-FIFO mode this bit is set when the transmit holding register (THR) is empty; it is
cleared when at a byte is written to the THR.
LSR[4]: Receive Break Flag
•
•
4.9
Logic 0 = Uses RTS# and CTS# pins for auto hardware flow control.
Logic 1 = Uses DTR# and DSR# pins for auto hardware flow control.
Logic 0 = Force RTS# output to a HIGH (default).
Logic 1= Force RTS# output to LOW.
Logic 0 = Force DTR# output to a HIGH (default).
Logic 1 = Force DTR# output to a LOW.
Logic 0 = No FIFO error (default).
Logic 1 = An indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or
break indication is in the FIFO data. This bit clears when there are no more errors in the FIFO.
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was LOW for one character frame time). In the FIFO
mode, only one break character is loaded into the FIFO. The break indication remains until the RX input
returns to the idle condition, “mark” or HIGH.
Line Status Register (LSR) - Read Only
Figure
12.
52
REV. 1.0.1