MFRC52201HN1,151 NXP Semiconductors, MFRC52201HN1,151 Datasheet - Page 18
MFRC52201HN1,151
Manufacturer Part Number
MFRC52201HN1,151
Description
IC READER 13.56MHZ 32-HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.MFRC52201HN1157.pdf
(109 pages)
Specifications of MFRC52201HN1,151
Rf Type
Read / Write
Frequency
13.56MHz
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935280547151
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Product data sheet
9.2.1.7 ErrorReg
Error bit register showing the error status of the last command executed.
Table 19:
Table 20:
[1]
Bit
7
6
5
4
3
2
1
0
Symbol
Access
Rights
Bit
Command execution will clear all error bits except for bit TempErr. A setting by software is impossible.
Symbol
WrErr
TempErr
-
BufferOvfl
CollErr
CRCErr
ParityErr
ProtocolErr
Description of ErrorReg bits
WrErr
ErrorReg register (address 06h); reset value: 00h
7
r
[1]
TempErr
6
r
Rev. 3.2 — 22 May 2007
Description
Set to logic 1, when data is written into the FIFO by the host during the
MFAuthent command or if data is written into the FIFO by the host
during the time between sending the last bit on the RF interface and
receiving the last bit on the RF interface.
Set to logic 1, if the internal temperature sensor detects overheating.
In this case, the antenna drivers are switched off automatically.
Reserved for future use.
Set to logic 1, if the host or a MFRC522’s internal state machine (e.g.
receiver) tries to write data into the FIFO buffer although the FIFO
buffer is already full.
Set to logic 1, if a bit-collision is detected. It is cleared automatically at
receiver start-up phase. This bit is only valid during the bitwise
anticollision at 106 kbit/s. During communication schemes at 212,
424 and 848 kbit/s this bit is always set to logic 0.
Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the
CRC calculation fails. It is cleared to logic 0 automatically at receiver
start-up phase.
Set to logic 1, if the parity check has failed. It is cleared automatically
at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE
communication at 106 kbit/s.
Set to logic 1, if one out of the following cases occur:
•
•
Set to logic 1 if the SOF is incorrect. It is cleared automatically at
receiver start-up phase. The bit is only valid for 106 kbit/s.
During the MFAuthent Command, bit ProtocolErr is set to logic 1,
if the number of bytes received in one data stream is incorrect.
RFU
5
-
BufferOvfl
4
r
CollErr
3
r
CRCErr
2
r
Contactless Reader IC
ParityErr ProtocolErr
MFRC522
© NXP B.V. 2007. All rights reserved.
1
r
18 of 109
0
r
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