MFRC52201HN1,151 NXP Semiconductors, MFRC52201HN1,151 Datasheet - Page 14
MFRC52201HN1,151
Manufacturer Part Number
MFRC52201HN1,151
Description
IC READER 13.56MHZ 32-HVQFN
Manufacturer
NXP Semiconductors
Datasheet
1.MFRC52201HN1157.pdf
(109 pages)
Specifications of MFRC52201HN1,151
Rf Type
Read / Write
Frequency
13.56MHz
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935280547151
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NXP Semiconductors
112132
Product data sheet
9.2.1.3 CommIEnReg
Table 9:
Table 10:
Control bits to enable and disable the passing of interrupt requests.
Table 11:
Table 12:
Bit
7 to 6
5
4
3 to 0
Bit
7
6
5
4
3
Symbol
Access
Symbol
Access
Rights
Rights
Bit
Bit
Symbol
IRqInv
TxIEn
RxIEn
IdleIEn
HiAlertIEn
Symbol
-
RcvOff
PowerDown
Command
Description of CommandReg bits
CommIEnReg register (address 02h); reset value: 80h
IRqInv
Description of CommIEnReg bits
CommandReg register (address 01h); reset value: 20h
r/w
7
7
RFU
-
Description
Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the
register Status1Reg.
Set to logic 0, the signal on pin IRQ is equal to bit IRq. In combination with
bit IRqPushPull in register DivIEnReg, the default value of logic 1 ensures,
that the output level on pin IRQ is tristate.
Allows the transmitter interrupt request (indicated by bit TxIRq) to be
propagated to pin IRQ.
Allows the receiver interrupt request (indicated by bit RxIRq) to be
propagated to pin IRQ.
Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to
pin IRQ.
Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be
propagated to pin IRQ.
TxIEn
r/w
6
Rev. 3.2 — 22 May 2007
6
Description
Reserved for future use.
Set to logic 1, the analog part of the receiver is switched off.
Set to logic 1, Soft Power-down mode is entered.
Set to logic 0, the MFRC522 starts the wake up procedure. During this
procedure this bit still shows a logic 1. A logic 0 indicates that the
MFRC522 is ready for operations; see
Power-down”.
Remark: The bit PowerDown cannot be set, when the command
Activates a command according to the Command Code. Reading this
register shows which command is actually executed (see
“MFRC522 Commands
RxIEn
RcvOff
r/w
5
r/w
5
SoftReset has been activated.
IdleIEn
Power Down
r/w
4
dy
4
Overview”).
HiAlertIEn LoAlertIEn
r/w
3
3
Section 16.2 “Soft
r/w
2
Contactless Reader IC
2
Command
MFRC522
dy
© NXP B.V. 2007. All rights reserved.
ErrIEn
r/w
1
1
Section 18.3
TimerIEn
14 of 109
r/w
0
0
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