M24LR64-RMN6T/2 STMicroelectronics, M24LR64-RMN6T/2 Datasheet - Page 30

• Manufacturer Part Number: M24LR64-RMN6T/2
• Description: 13.56MHZ 64KBIT EEPROM SO8N
• Manufacturer: STMicroelectronics

Specifications of M24LR64-RMN6T/2

• Featured Product: STM32 Cortex-M3 Companion Products
• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: 64 Kbit EEPROM
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Memory Size: 64 KB
• Organization: 2 K x 32
• Interface Type: I2C
• Maximum Clock Frequency: 400 KHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 600 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-10486-2

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2
C device operation
I
The device supports the I
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The M24LR64-R device is always a slave in
all communications.
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal write cycle.
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9
acknowledge the receipt of the eight data bits.
Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
2
C device operation
th
clock pulse period, the receiver pulls Serial Data (SDA) low to
2
C protocol. This is summarized in
Doc ID 15170 Rev 12
Figure
5. Any device that sends
M24LR64-R