M24LR64-RDW6T/2 STMicroelectronics, M24LR64-RDW6T/2 Datasheet
M24LR64-RDW6T/2
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M24LR64-RDW6T/2 Summary of contents
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... More than 1 Million write cycles ■ Multiple password protection in RF mode ■ Single password protection in I ■ More than 40-year data retention ■ Package – ECOPACK2 Halogen-free) Doc ID 15170 Rev 12 M24LR64-R SO8 (MN) 150 mils width 2 × TSSOP8 (DW mode ® (RoHS compliant and 1/128 www.st.com 1 ...
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... V ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SS 2.6 Supply voltage (V 2.6.1 2.6.2 2.6.3 2.6.4 3 User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 M24LR64-R RF block security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 Example of the M24LR64-R security protection . . . . . . . . . . . . . . . . . . . . 25 4.3 I2C_Write_Lock bit area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4 System parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5 M24LR64-R I 4.5.1 4.5 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 Start condition ...
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... Communication signal from VCD to M24LR64 Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1 Data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2 Data coding mode: 1 out 9.3 VCD to M24LR64-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.4 Start of frame (SOF Communications signal from M24LR64-R to VCD . . . . . . . . . . . . . . . . 47 10.1 Load modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.3 Data rates ...
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... Contents 11.4 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12 M24LR64-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.1 SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.2 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.3 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.4 SOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.5 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.6 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.7 EOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12 ...
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... Request parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 22 Request processing by the M24LR64 Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 24 Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 25 Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 25.1 t1: M24LR64-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 25.2 t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 25 VCD new request delay in the absence of a response from 3 the M24LR64 Commands codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 26 ...
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... Appendix A Anticollision algorithm (informative 123 A.1 Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Appendix B CRC (informative 124 B.1 CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 B.2 CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Appendix C Application family identifier (AFI) (informative 126 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6/128 Doc ID 15170 Rev 12 M24LR64-R ...
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... Table 18. UID format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 19. CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 20. VCD request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 21. M24LR64-R Response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 22. M24LR64-R response depending on Request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 23. General request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 24. Definition of request flags Table 25. Request flags when Bit Table 26. Request flags when Bit Table 27. ...
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... Fast Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . 108 Table 95. Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 96. Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 97. Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 98. Initiate Initiated response format 110 Table 99. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2 Table 100 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8/128 Doc ID 15170 Rev 12 M24LR64-R ...
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... M24LR64-R Table 101. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 102. Input parameters 112 2 Table 103 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2 Table 104 characteristics 114 Table 105. RF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 106. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 107. SO8N – 8-lead plastic small outline, 150 mils body width, package data 118 Table 108. UFDFPN8 (MLP8) – ...
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... End of frame, low data rate, one subcarriers Figure 45. End of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 46. End of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 47. M24LR64-R decision tree for AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10/128 = 400 kHz): maximum R value versus bus parasitic bus ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Doc ID 15170 Rev 12 ...
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... Write Single Block frame exchange between VCD and M24LR64 Figure 55. Read Multiple Block frame exchange between VCD and M24LR64- Figure 56. Select frame exchange between VCD and M24LR64 Figure 57. Reset to Ready frame exchange between VCD and M24LR64 Figure 58. Write AFI frame exchange between VCD and M24LR64 Figure 59 ...
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... Outgoing data are generated by the M24LR64-R load variation using Manchester coding with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data are transferred from the M24LR64-R at 6.6 Kbit/s in low data rate mode and 26 Kbit/s high data rate mode. The M24LR64-R supports the 53 Kbit/s in high data rate mode in one subcarrier frequency at 423 kHz ...
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... M24LR64-R Table 1. Signal names Signal name E0, E1 SDA SCL AC0, AC1 Figure 2. 8-pin package connections 1. See Package mechanical data Function Chip Enable Serial Data Serial Clock Antenna coils Supply voltage Ground AC0 AC1 3 6 SCL SDA section for package dimensions, and how to identify pin-1. ...
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... ISO 15693 and ISO 18000-3 mode 1 protocols. 14/128 indicates how the value of the pull-up resistor can be calculated). In Figure M24xxx M24xxx Doc ID 15170 Rev 12 M24LR64-R . (Figure 4 indicates how CC 3. When not connected (left Ai12806 or CC ...
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... Supply voltage (V This pin can be connected to an external DC supply voltage. Note: An internal voltage regulator allows the external voltage applied on V M24LR64-R, while preventing the internal power supply (rectified RF waveforms) to output a DC voltage on the V 2.6.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V ...
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... LOW f = 400 kHz), the R bus × C bus C V time constant must be below the 400 ns time constant line represented on the left. SCL I²C bus master SDA Stop Condition ACK ACK M24LR64 bus M24xxx C bus ai14796b Stop Condition AI00792B ...
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... Table 2. Device select code Device select code 1. The most significant bit, b7, is sent first and E1 are compared against the respective external pins on the memory device not connected to any external pin however used to address the M24LR64-R as described in Section 3 and Section Table 3. Address most significant byte ...
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... Read and write operations are possible if the addressed data are not in a protected sector. The M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier (UID). The UID is compliant with the ISO 15963 description, and its value is used during the anticollision sequence (Inventory) ...
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... Figure 7. Memory sector organization Sector details The M24LR64-R user memory is divided into 64 sectors. Each sector contains 1024 bits. The protection scheme is described mode, a sector provides 32 blocks of 32 bits. Each read and write access are done by block. Read and write block accesses are controlled by a Sector Security Status byte that defines the access rights to all the 32 blocks contained in the sector ...
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... Doc ID 15170 Rev 12 M24LR64-R Bits [23:16] Bits [15:8] Bits [7:0] user user user user user user user user user user user user user user user ...
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... M24LR64-R Table 5. Sector details (continued) Sector RF block number address ... byte Bits [31:24] address 128 user 132 user 136 user 140 user 144 user 148 user 152 user 156 user ... ... ... ... ... ... Doc ID 15170 Rev 12 User memory organization Bits [23:16] Bits [15:8] Bits [7:0] ...
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... Doc ID 15170 Rev 12 M24LR64-R Bits [15:8] Bits [7:0] user user user user user user user user user user user user user user user user ...
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... M24LR64-R RF block security The M24LR64-R provides a special protection mechanism based on passwords. Each memory sector of the M24LR64-R can be individually protected by one out of three available passwords, and each sector can also have Read/Write access conditions set. Each memory sector of the M24LR64-R is assigned with a Sector security status byte ...
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... Table 9. Password Control bits The M24LR64-R password protection is organized around a dedicated set of commands plus a system area of three password blocks where the password values are stored. This system area is described in Table 10. Password system area Add The dedicated password commands are: ● ...
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... Present-sector Password: The Present-sector Password command is used to present one of the three passwords to the M24LR64-R in order to modify the access rights of all the memory sectors linked to that password correct, the access rights remain activated until the tag is powered off or until a new Present-sector Password command is issued. If the presented password value is not correct, all the access rights of all the memory sectors are deactivated. ● ...
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... 2048 2052 4.4 System parameters The M24LR64-R provides the system area required by the ISO 15693 RF protocol, as shown in Table 14. The first 32-bit block starting from I is used to activate/deactivate the write protection of the protected sector in I power-on, all user memory sectors protected by the I2C_Write_Lock bits can be read but cannot be modified ...
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... M24LR64-R in order to modify the write access rights of all the memory sectors protected by the I2C_Write_Lock bits, including the password itself. If the presented password is correct, the access rights remain activated until the M24LR64-R is powered off or until a new I Present Password command is issued. Following a Start condition, the bus master sends a device select code with the Read/Write bit (RW) reset to 0 and the Chip Enable bit ...
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... I C Write Password command description 2 The I C Write Password command is used to write a 32-bit block into the M24LR64-R I password system area. This command is used in I value. It cannot be used to update any of the RF passwords. After the write cycle, the new password value is automatically activated. The I ...
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... M24LR64-R 2 Figure Write Password command Ack Device select Password code address 09h R/W Ack Ack New password Validation [31:24] code 07h Device select code = 1010 Ack generated during 9 bit time slot. Ack Ack Ack Password New password New password address 00h ...
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... The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24LR64-R device is always a slave in all communications. ...
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... M24LR64-R 5.5 Memory addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). ...
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... After each byte is transferred, the internal byte address counter (inside the page) is incremented. The transfer is terminated by the bus master generating a Stop condition. 32/128 , and the successful completion of a Write operation, W Figure 11. Doc ID 15170 Rev 12 M24LR64-R Figure 11, and waits for two (Table 4). Bits b15 to b0 form th ...
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... M24LR64-R Figure 11. Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled) ACK Byte Write Dev Select R/W ACK Page Write Dev Select R/W Figure 12. Write cycle polling flowchart using ACK First byte of instruction with already decoded by the device ReStart Stop ACK ...
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... Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). 34/128 , but the typical time is shorter. To make use of this, a polling sequence Figure 12, is: Doc ID 15170 Rev 12 M24LR64 ...
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... M24LR64-R Figure 13. Read mode sequences Current Address Read Random Address Read Sequential Current Read Sequential Random Read 1. The seven most significant bits of the device select code of a Random Read (in the 1 be identical. ACK NO ACK Dev select Data out R/W ACK ACK ...
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... For all Read commands, the device waits, after each byte read, for an acknowledgment th during the 9 bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode. 36/128 Figure 13. Doc ID 15170 Rev 12 M24LR64-R ...
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... The device is delivered with all bits in the user memory array set to 1 (each byte contains FFh device operation The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in sector can be individually read- and/or write-protected using a specific lock or password command. Read and Write operations are possible if the addressed block is not protected. During a Write, the 32 bits of the block are replaced by the new 32-bit value ...
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... The M24LR64-R supports the following commands: ● Inventory, used to perform the anticollision sequence. ● Stay Quiet, used to put the M24LR64-R in quiet mode, where it does not respond to any inventory command. ● Select, used to select the M24LR64-R. After this command, the M24LR64-R processes all Read/Write commands with Select_flag set. ...
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... Power transfer Power is transferred to the M24LR64-R by radio frequency at 13.56 MHz via coupling antennas in the M24LR64-R and the VCD. The RF operating field of the VCD is transformed on the M24LR64-R antenna Voltage which is rectified, filtered and internally regulated. The amplitude modulation (ASK) on this received signal is demodulated by the ASK demodulator ...
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... The modulation index is defined as [a – b]/[ where a is the peak signal amplitude and b, the minimum signal amplitude of the carrier frequency. Depending on the choice made by the VCD, a “pause” will be created as described in Figure 14 and Figure The M24LR64-R is operational for any degree of modulation index from between 10% and 30%. Figure 14. 100% modulation waveform Carrier Amplitude 105% ...
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... Amplitude Amplitude Modulation Modulation Modulation Index Index Index The VICC shall be operational for any value of modulation index between 10 % and 30 %. Communication signal from VCD to M24LR64-R Parameter definition 0 – – Min Min Min Max Max Max 6,0 µs 6,0 µs 6,0 µs 9,44 µ ...
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... Data rate and data coding The data coding implemented in the M24LR64-R uses pulse position modulation. Both data coding modes that are described in the ISO15693 are supported by the M24LR64-R. The selection is made by the VCD and indicated to the M24LR64-R within the start of frame (SOF). 9.1 Data coding mode: 1 out of 256 The value of one single byte is represented by the position of one pause ...
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... M24LR64-R Figure 17. Detail of a time period Pulse Modulated Carrier . . 9.2 Data coding mode: 1 out of 4 The value of 2 bits is represented by the position of one pause. The position of the pause successive time periods of 18.88 µs (256/f successive pairs of bits form a byte, where the least significant pair of bits is transmitted first. ...
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... Figure 19. 1 out of 4 coding example 10 75.52 µs 44/128 75.52 µs 28.32 µs 9.44 µs 75.52 µs 47.20µs 75.52 µs 75.52 µ 75.52 µs 75.52 µs Doc ID 15170 Rev 12 M24LR64-R 9.44 µs 66.08 µs 9.44 µs AI06658 11 75.52 µs AI06659 ...
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... The M24LR64-R is ready to receive a new command frame from the VCD 311.5 µs (t sending a response frame to the VCD. The M24LR64-R takes a power-up time of 0.1 ms after being activated by the powering field. After this delay, the M24LR64-R is ready to receive a command frame from the VCD. ...
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... Data rate and data coding Figure 22. EOF for either data coding mode 46/128 9.44 µs 9.44 µs 37.76 µs Doc ID 15170 Rev 12 M24LR64-R AI06662 ...
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... Data rates The M24LR64-R can respond using the low or the high data rate format. The selection of the data rate is made by the VCD using the second bit in the protocol header. It also supports the x2 mode available on all the Fast commands. ...
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... For the Fast commands, a logic 1 starts with an unmodulated time of 9.44 µs followed by 4 pulses of 423.75 kHz (f Figure 26. Logic 1, high data rate x2 48/128 /32) followed by an unmodulated time of C Figure 23. 37.76µs Figure 24. 18.88µs Figure 25. 37.76µs /32) as shown in Figure 26. C 18.88µs Doc ID 15170 Rev 12 M24LR64-R ai12076 /32) followed ai12066 ai12077 ai12067 ...
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... M24LR64-R 11.1.2 Low data rate A logic 0 starts with 32 pulses at 423.75 kHz (f 75.52 µs as shown in Figure 27. Logic 0, low data rate For the Fast commands, a logic 0 starts with 16 pulses at 423.75 kHz (f unmodulated time of 37.76 µs as shown in Figure 28. Logic 0, low data rate x2 A logic 1 starts with an unmodulated time of 75.52 µs followed by 32 pulses at 423.75 kHz ...
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... C Figure 33. For the Fast commands, the x2 mode is not available. 149.84µs /28) followed by 32 pulses at 423.75 kHz C Figure 34. For the Fast commands, the x2 mode is not available. 149.84µs Doc ID 15170 Rev 12 M24LR64-R ai12074 ai12073 ai12072 ai12075 ...
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... Figure 37. Start of frame, low data rate, one subcarrier Figure 35. 113.28µs /32), and a logic 1 that consists of an unmodulated time of C Figure 56.64µs Figure 37. 453.12µs Doc ID 15170 Rev 12 M24LR64-R to VCD frames 37.76µs ai12078 36. 18.88µs ai12079 151.04µs ai12080 51/128 ...
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... M24LR64-R to VCD frames For the Fast commands, the SOF comprises an unmodulated time of 113.28 µs, followed by 48 pulses at 423.75 kHz (f followed by 16 pulses at 423.75 kHz as shown in Figure 38. Start of frame, low data rate, one subcarrier x2 12.4 SOF when using two subcarriers 12.5 High data rate The SOF comprises 27 pulses at 484 ...
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... Figure 44. End of frame, low data rate, one subcarriers x2 C Figure 41. Figure 42. 56.64µs 18.88µs Figure 43. Figure 44. 75.52µs 226.56µs Doc ID 15170 Rev 12 M24LR64-R to VCD frames /32), and by an unmodulated time of 113.28µs /32) and an C ai12085 /32) and an unmodulated time of C 453.12µs /32) and an C ai12087 ai12084 ai12086 53/128 ...
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... M24LR64-R to VCD frames 12.10 EOF when using two subcarriers 12.11 High data rate The EOF comprises a logic 0 that includes 8 pulses at 423.75 kHz and 9 pulses at 484.28 kHz, followed by 24 pulses at 423.75 kHz (f (f /28) as shown in C For the Fast commands, the x2 mode is not available. ...
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... M24LR64-R 13 Unique identifier (UID) The M24LR64-R is uniquely identified by a 64-bit unique identifier (UID). This UID complies with ISO/IEC 15963 and ISO/IEC 7816-6. The UID is a read-only code and comprises: ● 8 MSBs with a value of E0h ● The IC manufacturer code of ST 02h bits (ISO/IEC 7816-6/AM1) ● ...
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... Application family identifier (AFI) The AFI (application family identifier) represents the type of application targeted by the VCD and is used to identify, among all the M24LR64-Rs present, only the M24LR64-Rs that meet the required application criteria. Figure 47. M24LR64-R decision tree for AFI The AFI is programmed by the M24LR64-R issuer (or purchaser) in the AFI register. Once programmed and Locked, it can no longer be modified ...
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... EOF. The CRC is calculated on all the bytes after the SOF up to the CRC field. Upon reception of a request from the VCD, the M24LR64-R verifies that the CRC value is valid invalid, the M24LR64-R discards the frame and does not answer to the VCD. Upon reception of a Response from the M24LR64- recommended that the VCD verifies whether the CRC value is valid ...
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... M24LR64-R protocol description The transmission protocol (or simply protocol) defines the mechanism used to exchange instructions and data between the VCD and the M24LR64-R, in both directions based on the concept of “VCD talks first”. This means that an M24LR64-R will not start transmitting unless it has received and properly decoded an instruction sent by the VCD. The protocol is based on an exchange of: ● ...
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... M24LR64-R Figure 48. M24LR64-R protocol timing Request VCD (Table M24LR64 -R Timing frame 20) Response frame (Table 21) <-t -> <-t 1 Doc ID 15170 Rev 12 M24LR64-R protocol description Request frame (Table 20) Response frame (Table -> <-t -> 21) <-t -> 2 59/128 ...
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... Table 22: M24LR64-R response depending on 17.1 Power-off state The M24LR64 the Power-off state when it does not receive enough energy from the VCD. 17.2 Ready state The M24LR64 the Ready state when it receives enough energy from the VCD. When in the Ready state, the M24LR64-R answers any request where the Select_flag is not set. ...
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... The M24LR64-R returns to the “Power Off” state only when both conditions are met: the V supplied ( HiZ) and the tag is out of the RF field. Please refer to application note AN3057 for more information. 2. The intention of the state transition method is that only one M24LR64-R should be in the selected state at a time. Address_flag ...
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... Modes 18 Modes The term “mode” refers to the mechanism used in a request to specify the set of M24LR64- Rs that will answer the request. 18.1 Addressed mode When the Address_flag is set to 1 (Addressed mode), the request contains the Unique ID (UID) of the addressed M24LR64-R. Any M24LR64-R that receives a request with the Address_flag set to 1 compares the received Unique ID to its own ...
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... The flags field consists of eight bits. The bit 3 (Inventory_flag) of the request flag defines the contents of the 4 MSBs (bits 5 to 8). When bit 3 is reset (0), bits define the M24LR64- R selection criteria. When bit 3 is set (1), bits define the M24LR64-R Inventory parameters ...
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... Request is executed only by the M24LR64-R in Selected state Request is not addressed. UID field is not present. The request is 0 executed by all M24LR64-Rs. Request is addressed. UID field is present. The request is executed 1 only by the M24LR64-R whose UID matches the UID specified in the request. 0 Option not activated. 1 Option activated. ...
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... General response format S O Response_flags F 20.1 Response flags In a response, the flags indicate how actions have been performed by the M24LR64-R and whether corresponding fields are present or not. The response flags consist of eight bits. Table 28. Definitions of response flags Bit No Bit 1 Error_flag Bit 2 ...
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... Response format 20.2 Response error code If the Error_flag is set by the M24LR64-R in the response, the Error code field is present and provides information about the error that occurred. Error codes not specified in Table 29. Response error code definition Error code 02h 03h 0Fh 10h ...
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... M24LR64-R 21 Anticollision The purpose of the anticollision sequence is to inventory the M24LR64-Rs present in the VCD field using their unique ID (UID). The VCD is the master of communications with one or several M24LR64-Rs. It initiates M24LR64-R communication by issuing the Inventory request. The M24LR64-R sends its response in the determined slot or does not respond. ...
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... The first slot starts immediately after the reception of the request EOF. To switch to the next slot, the VCD sends an EOF. The following rules and restrictions apply: ● M24LR64-R answer is detected, the VCD may switch to the next slot by sending an EOF, ● if one or more M24LR64-R answers are detected, the VCD waits until the complete frame has been received before sending an EOF for switching to the next slot ...
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... M24LR64-R 22 Request processing by the M24LR64-R Upon reception of a valid request, the M24LR64-R performs the following algorithm: ● NbS is the total number of slots (1 or 16) ● the current slot number (0 to 15) ● LSB (value, n) function returns the n Less Significant Bits of value ● MSB (value, n) function returns the n Most Significant Bits of value ● ...
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... The VCD sends an Inventory request frame terminated by an EOF. The number of slots is 16. ● M24LR64-R_1 transmits its response in Slot the only one to do so, therefore no collision occurs and its UID is received and registered by the VCD; ● The VCD sends an EOF in order to switch to the next slot. ...
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... M24LR64-R Figure 51. Description of a possible anticollision sequence Explanation of the possible cases Doc ID 15170 Rev 12 71/128 ...
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... Inventory Initiated command 24 Inventory Initiated command The M24LR64-R provides a special feature to improve the inventory time response of moving tags using the Initiate_flag value. This flag, controlled by the Initiate command, allows tags to answer to Inventory Initiated commands. For applications in which multiple tags are moving in front of a reader possible to miss tags using the standard inventory command ...
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... EOF from the M24LR64-Rs. The EOF sent by the VCD may be either 10% or 100% modulated regardless of the modulation index used for transmitting the VCD request to the M24LR64- also the time after which the VCD may send a new request to the M24LR64 described in Table 48: M24LR64-R protocol ...
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... Commands codes 26 Commands codes The M24LR64-R supports the commands described in this section. Their codes are given in Table 33. Table 33. Command codes Command code standard 01h 02h 20h 21h 23h 25h 26h 27h 28h 29h 2Ah 2Bh 74/128 Function Inventory Stay Quiet Read Single Block ...
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... Inventory response format Response Response_ SOF flags 8 bits During an Inventory process, if the VCD does not receive an RF M24LR64-R response, it waits a time t before sending an EOF to switch to the next slot the request EOF sent by the VCD. ● If the VCD sends a 100% modulated EOF, the minimum value of t ...
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... Stay Quiet Command code = 0x02 On receiving the Stay Quiet command, the M24LR64-R enters the Quiet State if no error occurs, and does NOT send back a response. There is NO response to the Stay Quiet command even if an error occurs. When in the Quiet state: ● ...
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... On receiving the Read Single Block command, the M24LR64-R reads the requested block and sends back its 32-bit value in the response. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag the M24LR64-R answers with an error code. The Option_flag is supported. ...
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... Figure 53. Read Single Block frame exchange between VCD and M24LR64-R VCD SOF M24LR64- R 78/128 Read Single Block ...
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... The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag the M24LR64-R answers with an error code. The Option_flag is supported. During the RF write cycle W Otherwise, the M24LR64-R may not program correctly the data into the memory. The W time is equal to t 1nom Table 41. ...
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... Commands codes Figure 54. Write Single Block frame exchange between VCD and M24LR64-R Write Single VCD SOF Block request M24LR64-R M24LR64-R 80/128 EOF Write Single <-t -> SOF 1 Block response <------------------- W ---------------> SOF t Doc ID 15170 Rev 12 M24LR64-R Write sequence when EOF error Write Single ...
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... If the number of blocks overlaps sectors, the M24LR64-R returns an error code. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag the M24LR64-R answers with an error code. ...
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... Figure 55. Read Multiple Block frame exchange between VCD and M24LR64-R VCD M24LR64-R 82/128 Response_flags Error code 8 bits ...
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... UID does not match its own, the selected M24LR64-R returns to the Ready state and does not send a response. The M24LR64-R answers an error code only if the UID is equal to its own UID. If not, no response is generated error occurs, the M24LR64-R remains in its current state. ...
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... Commands codes 26.7 Reset to Ready On receiving a Reset to Ready command, the M24LR64-R returns to the Ready state if no error occurs. In the Addressed mode, the M24LR64-R answers an error code only if the UID is equal to its own UID. If not, no response is generated. Table 51. Reset to Ready request format ...
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... On receiving the Write AFI request, the M24LR64-R programs the 8-bit AFI value to its memory. The Option_flag is supported. During the RF write cycle W Otherwise, the M24LR64-R may not write correctly the AFI value into the memory. The W time is equal to t 1nom Table 54. ...
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... Commands codes Figure 58. Write AFI frame exchange between VCD and M24LR64-R VCD SOF M24LR64-R M24LR64-R 86/128 Write AFI EOF request <-t -> SOF 1 <------------------ W Doc ID 15170 Rev 12 M24LR64-R Write AFI Write sequence EOF response when error Write AFI --------------> SOF t response EOF ...
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... Lock AFI On receiving the Lock AFI request, the M24LR64-R locks the AFI value permanently. The Option_flag is supported. During the RF write cycle W Otherwise, the M24LR64-R may not Lock correctly the AFI value in memory. The W equal × 302 µs. 1nom Table 57. ...
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... Commands codes Figure 59. Lock AFI frame exchange between VCD and M24LR64-R VCD M24LR64-R M24LR64-R 88/128 Lock AFI SOF EOF request <-t -> SOF 1 <----------------- W Doc ID 15170 Rev 12 M24LR64-R Lock AFI Lock sequence EOF response when error Lock AFI -------------> SOF t response EOF ...
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... Write DSFID On receiving the Write DSFID request, the M24LR64-R programs the 8-bit DSFID value to its memory. The Option_flag is supported. During the RF write cycle W Otherwise, the M24LR64-R may not write correctly the DSFID value in memory. The W is equal × 302 µs. 1nom Table 60 ...
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... Commands codes Figure 60. Write DSFID frame exchange between VCD and M24LR64-R VCD SOF M24LR64-R M24LR64-R 90/128 Write DSFID EOF request <-t -> SOF 1 <---------------- W Doc ID 15170 Rev 12 M24LR64-R Write DSFID Write sequence EOF response when error Write DSFID ------------> SOF t response EOF ...
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... Lock DSFID On receiving the Lock DSFID request, the M24LR64-R locks the DSFID value permanently. The Option_flag is supported. During the RF write cycle W Otherwise, the M24LR64-R may not lock correctly the DSFID value in memory. The W is equal × 302 µs. 1nom Table 63. ...
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... Commands codes Figure 61. Lock DSFID frame exchange between VCD and M24LR64-R VCD SOF M24LR64-R M24LR64-R 92/128 Lock DSFID EOF request <-t -> SOF 1 <----------------- W Doc ID 15170 Rev 12 M24LR64-R Lock DSFID Lock sequence EOF response when error Lock -------------> SOF DSFID t response EOF ...
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... Option_flag is supported and must be reset to 0. The Get System Info can be issued in both Addressed and Non Addressed modes. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag the M24LR64-R answers with an error code. Table 66. ...
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... Commands codes Figure 62. Get System Info frame exchange between VCD and M24LR64-R VCD SOF M24LR64 -R 94/128 Get System Info EOF request <-t -> SOF Get System Info response EOF 1 Doc ID 15170 Rev 12 M24LR64-R ...
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... For example, a value of '06' in the “Number of blocks” field requests to return the security status of 7 blocks. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag the M24LR64-R answers with an error code. ...
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... Figure 63. Get Multiple Block Security Status frame exchange between VCD and M24LR64-R VCD SOF M24LR64 -R 96/128 Error code 8 bits Get Multiple Block EOF Security Status <-t -> SOF 1 Doc ID 15170 Rev 12 M24LR64-R Response CRC16 EOF 16 bits Get Multiple Block EOF Security Status ...
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... On receiving the Write-sector Password command, the M24LR64-R uses the data contained in the request to write the password and reports whether the operation was successful in the response. The Option_flag is supported. During the RF write cycle time, W 10%). Otherwise, the M24LR64-R may not correctly program the data into the memory. The W time is equal selected password is automatically activated ...
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... Commands codes Figure 64. Write-sector Password frame exchange between VCD and M24LR64-R VCD SOF M24LR64-R M24LR64-R 98/128 Write- sector EOF Password request <-t -> SOF 1 <----------------- W Doc ID 15170 Rev 12 M24LR64-R Write-sector Write sequence Password EOF when error response Write- sector -------------> SOF t Password response ...
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... Care must be taken when issuing the Lock-sector Password command as all the blocks belonging to the same sector are automatically locked by a single command. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag the M24LR64-R answers with an error code. During the RF write cycle W otherwise, the M24LR64-R may not correctly lock the memory block ...
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... Figure 65. Lock-sector Password frame exchange between VCD and M24LR64-R VCD SOF M24LR64-R M24LR64-R 100/128 ...
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... On receiving the Present-sector Password command, the M24LR64-R compares the requested password with the data contained in the request and reports whether the operation has been successful in the response. The Option_flag is supported. During the comparison cycle equal to W 10%) otherwise, the M24LR64-R the Password value may not be correctly compared. The W time is equal ...
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... Commands codes Figure 66. Present-sector Password frame exchange between VCD and M24LR64-R VCD M24LR64-R M24LR64-R 102/128 Present- sector SOF EOF Password request <-t -> SOF 1 <---------------- W Doc ID 15170 Rev 12 M24LR64-R Present- sector sequence when EOF Password error response Present- sector ------------> SOF t Password response ...
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... On receiving the Fast Read Single Block command, the M24LR64-R reads the requested block and sends back its 32-bit value in the response. The Option_flag is supported. The data rate of the response is multiplied by 2. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag the M24LR64-R answers with an error code. Table 83. ...
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... Figure 67. Fast Read Single Block frame exchange between VCD and M24LR64-R VCD SOF M24LR64 -R 104/128 Fast Read Single Block ...
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... Fast Inventory Initiated Before receiving the Fast Inventory Initiated command, the M24LR64-R must have received an Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR64-R does not answer to the Fast Inventory Initiated command. On receiving the Fast Inventory Initiated request, the M24LR64-R runs the anticollision sequence ...
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... Ready state. The command has to be issued in the Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0 error occurs, the M24LR64-R does not generate any answer. The Initiate_flag is reset after a power off of the M24LR64-R. The data rate of the response is multiplied by 2. The request contains: ● ...
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... If the number of blocks overlaps sectors, the M24LR64-R returns an error code. The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag the M24LR64-R answers with an error code. ...
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... Fast Read Multiple Block response format when Error_flag is set Response SOF Response parameter: ● Error code as Error_flag is set: – 0Fh: other error – 10h: block address not available Figure 69. Fast Read Multiple Block frame exchange between VCD and M24LR64-R VCD M24LR64-R 108/128 Response_flags Error code 8 bits 8 bits Fast Read ...
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... Inventory Initiated Before receiving the Inventory Initiated command, the M24LR64-R must have received an Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR64-R does not answer to the Inventory Initiated command. On receiving the Inventory Initiated request, the M24LR64-R runs the anticollision sequence ...
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... The command has to be issued in the Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0 error occurs, the M24LR64-R does not generate any answer. The Initiate_flag is reset after a power off of the M24LR64-R. ...
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... Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 3. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A 100 pF 1500 500 required by the IEC 61000-4-2 method. M24LR64-R is mounted on ST’s reference antenna ANT1- M24LR-A. Parameter Sawn wafer on UV ...
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... Pulse width ignored (Input filter on SCL and SDA Characterized only. 112/128 2 C mode. The parameters in the DC and AC characteristic Parameter Parameter Input Levels Timing Reference Levels 0.8V CC 0.2V CC Parameter Doc ID 15170 Rev 12 M24LR64-R Min. Max. Unit 1.8 5.5 V –40 85 °C Min. Max. Unit 100 ...
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... M24LR64-R 2 Table 103 characteristics Symbol Input leakage current I LI (SCL, SDA, E1, E0) I Output leakage current LO I Supply current (Read Supply current (Write) CC0 I Standby supply current CC1 Input low voltage (SDA SCL) Input high voltage (SDA SCL) V Output low voltage OL 1. SCL, SDA according to AC input waveform 2 ...
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... Clock low to next data valid (access time) Start condition set up time Start condition hold time Stop condition set up time Time between Stop condition and next Start condition I²C write time 2 C specification (which specifies t Figure 4 Doc ID 15170 Rev 12 M24LR64-R Table 100 Min. Max. 400 600 1300 20 300 20 ...
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... M24LR64-R 2 Figure 72 waveforms tXL1XL2 tXH1XH2 SCL tDLCL SDA In tCHDL tXH1XH2 Start condition SCL SDA In tCHDH Stop condition tCHCL SCL tCLQV SDA Out tCHCL tCLCH tCLDX tDXCH SDA Change SDA Input tW Write cycle tCLQX Data valid Data valid Doc ID 15170 Rev and AC parameters ...
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... RFSBL for bit Minimum time from carrier t MIN CD generation to first data f Subcarrier frequency high SH f Subcarrier frequency low SL t Time for M24LR64-R response 4224 Time between commands 2 RF write time (including W t internal Verify) 116/128 (1) (2) Condition ° ° – ...
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... Table 106. Operating conditions Symbol T Ambient operating temperature A Figure 73 shows an ASK modulated signal, from the VCD to the M24LR64-R. The test condition for the AC/DC parameters are: ● Close coupling condition with tester antenna (1 mm) ● M24LR64-R performance measured at the tag antenna Figure 73 ...
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... Doc ID 15170 Rev 45˚ c 0.25 mm GAUGE PLANE SO-A (1) inches Typ Min 0.0039 0.0492 0.0110 0.0067 0.1929 0.1890 0.2362 0.2283 0.1535 0.1496 0.0500 – 0° 0.0157 0.0410 M24LR64-R ® Max 0.0689 0.0098 0.0189 0.0091 0.0039 0.1969 0.2441 0.1575 – 8° 0.0500 ...
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... M24LR64-R Figure 75. UFDFPN8 (MLP8) – Ultra thin fine pitch dual flat package no lead mm, package outline 1. Drawing is not to scale. Table 108. UFDFPN8 (MLP8) – Ultra thin fine pitch dual flat package no lead mm, package mechanical data Symbol (2) ddd 1. Values in inches are converted from mm and rounded to 4 decimal digits. ...
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... Doc ID 15170 Rev 12 M24LR64 TSSOP8AM inches (1) Typ Min Max 0.0472 0.002 0.0059 0.0394 0.0315 0.0413 0.0075 0.0118 0.0035 0.0079 0.0039 0.1181 0.1142 0.122 ...
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... M24LR64-R 31 Part numbering Table 110. Ordering information scheme for packaged devices Example: Device type M24LR64 = Dual interface EEPROM Operating voltage 1 Package MN = SO8N (150 mils width UFDFPN8 (MLP8 TSSOP8 Device grade 6 = industrial: device tested with standard test flow over – °C ...
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... Part numbering Table 111. Ordering information scheme for bare die devices Example: Device type M24LR64 = Dual interface EEPROM Operating voltage 1 Packing S = Sawn wafer (inkless tape Z = Sawn wafer (inked tape Wafer orientation 1 = see Note 1 Wafer size in inches 8 = 8-inch wafer (see Wafer thickness 5 = 140 µ ...
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... M24LR64-R is inventoried then store (M24LR64-R_UID) else ; remember a collision was detected push(mask,address) endif next sub_address if stack_not_empty ...
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... B.1 CRC error detection method The cyclic redundancy check (CRC) is calculated on all data contained in a message, from the start of the flags through to the end of Data. The CRC is used from VCD to M24LR64-R and from M24LR64-R to VCD. Table 112. CRC definition CRC type ...
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... M24LR64-R number_of_databytes = NUMBER_OF_BYTES; } else // check CRC { number_of_databytes = NUMBER_OF_BYTES + 2; } current_crc_value = PRESET_VALUE; for ( < number_of_databytes; i++) { current_crc_value = current_crc_value ^ ((unsigned int)array_of_databytes[i]); for ( < 8; j++) { if (current_crc_value & 0x0001) { POLYNOMIAL; } else { } } } if (calculate_or_check_crc == CALC_CRC) { current_crc_value = ~current_crc_value; printf ("Generated CRC is 0x%04X\n", current_crc_value); // current_crc_value is now ready to be appended to the data stream ...
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... Application family identifier (AF (informative) The AFI (application family identifier) represents the type of application targeted by the VCD and is used to extract from all the M24LR64-R present only the M24LR64-R meeting the required application criteria programmed by the M24LR64-R issuer (the purchaser of the M24LR64-R). Once locked, it cannot be modified ...
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... M24LR64-R Revision history Table 114. Document revision history Date 26-Feb-2010 06-Apr-2010 24-Jun-2010 09-Aug-2010 02-Dec-2010 Revision Previous revisions: design and engineering phase. 8 Initial public release. Updated Section 28 and 9 characterisation Added 8” wafer delivery form and update endurance on cover page. Updated V overview and replaced diode by regulator in CC Section 2 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 128/128 Please Read Carefully: © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID 15170 Rev 12 M24LR64-R ...