ADF7010BRUZ-REEL Analog Devices Inc, ADF7010BRUZ-REEL Datasheet - Page 19

• Manufacturer Part Number: ADF7010BRUZ-REEL
• Description: IC XMITTER ASK/FSK/GFSK 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of ADF7010BRUZ-REEL

• Frequency: 902MHz ~ 928MHz
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Modulation Or Protocol: ASK, FSK, GFSK
• Data Rate - Maximum: 76.8 kbps
• Power - Output: -16dBm ~ 12dBm
• Current - Transmitting: 40mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

The N divide in the integer part is also reduced. This results in
less noise being multiplied from the PFD to the output, resulting
in better phase noise for higher PFDs.
Increasing the PFD reduces your resolution at the output.
MODULATION SCHEMES
Frequency Shift Keying (FSK)
Frequency shift keying is implemented by setting the N value
for the center frequency and then toggling this with the TxDATA
line. The deviation from the center frequency is set using Bits
D1–D7 in the Modulation register. The deviation from the center
frequency in Hz is:
The modulation number is a number from 1 to 127. FSK is selected
by setting Bits S1 and S2 to zero in the modulation register.
Gaussian Frequency Shift Keying (GFSK)
Gaussian frequency shift keying reduces the bandwidth occupied
by the transmitted spectrum by digitally prefiltering the TxDATA.
A TxCLK output line is provided from the ADF7010 for syn-
chronization of TxDATA from the microcontroller. The TxCLK
line may be connected to the clock input of an external shift
register that clocks data to the transmitter at the exact data rate.
REV. 0
TxDATA
DATA FROM
MICROCONTROLLER
–F
+F
FSK DEVIATION
FREQUENCY
DEV
DEV
Figure 14. TxCLK Pin Synchronizing Data for GFSK
CHEAP AT CRYSTAL
F
DEVIATION
Figure 13. FSK Implementation
FRACTIONAL N
R
REGISTER
(
Hz
CHARGE
SHIFT
PUMP
PFD/
) =
THIRD ORDER
MODULATOR
Modulation Number
INTERNAL VCO USING
SPIRAL INDUCTORS
GAIN 70 MHz/V – 90 MHz/V
TxDATA
TxCLK
-
2
12
INTEGER N
ADF7010
VCO
¥
F
PFD
ANTENNA
PA STAGE
–19–
Setting up the ADF7010 for GFSK
To set up the frequency deviation, set the PFD and the mod
control Bits MC1 to MC3:
where m is mod control.
To set up the GFSK data rate:
For further information, refer to the Using GFSK on the ADF7010
application note.
Amplitude Shift Keying (ASK)
Amplitude shift keying is implemented by switching the output
stage between two discrete power levels. This is implemented by
toggling the DAC, which controls the output level between two
7-bit values set up in the Modulation register. A zero TxDATA
bit sends Bits D1–D7 to the DAC. A high TxDATA bit sends
Bits P1–P7 to the DAC. A maximum modulation depth of 30 dB
is possible. ASK is selected by setting Bit S2 = 1 and Bit S1 = 0.
On-Off Keying (OOK)
On-off keying is implemented by switching the output stage to a
certain power level for a high TxDATA bit and switching the
output stage off for a zero. Due to feedthrough effects, a maxi-
mum modulation depth of 33 dB is specified. For OOK, the
transmitted power for a high input is programmed using Bits
P1–P7 in the Modulation register. OOK is selected by setting
Bits S1 and S2 to 1 in the modulation register.
CHOOSING CHANNELS FOR BEST SYSTEM
PERFORMANCE
The fractional-N PLL allows the selection of any channel within
902 MHz to 928 MHz to a resolution of < 100 Hz, as well as
facilitating frequency hopping systems. The use of the ADF7010
in accordance with FCC Part 15.247, allows for improved range
by allowing power levels up to 1 W, and greater interference
avoidance by changing the RF channel on a regular basis.
Careful selection of the RF transmit channels must be made
to achieve best spurious performance. The architecture of
Fractional-N results in some level of the nearest integer channel
moving through the loop to the RF output. These “beat-note”
spurs are not attenuated by the loop if the desired RF channel
and the nearest integer channel are separated by a frequency of
less than the loop BW.
The occurrence of beat-note spurs is rare, as the integer frequen-
cies are at multiples of the reference, which is typically > 10 MHz.
The beat-note spurs can be significantly reduced in amplitude by
avoiding very small or very large values in the fractional register.
By having a channel 1 MHz away from an integer frequency, a
100 kHz loop filter will reduce the level to < –45 dBc. When using
an external VCO, the Fast Lock (bleed) function will reduce the
spurs to < –60 dBc for the same conditions above.
Data Rate bits s
GFSK
(
DEVIATION
) =
Divider Factor
(
Hz
) =
2
F
m
PFD
¥
¥
2
Index Counter
12
F
ADF7010
PFD