ADF7010BRUZ-REEL Analog Devices Inc, ADF7010BRUZ-REEL Datasheet - Page 17

• Manufacturer Part Number: ADF7010BRUZ-REEL
• Description: IC XMITTER ASK/FSK/GFSK 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of ADF7010BRUZ-REEL

• Frequency: 902MHz ~ 928MHz
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Modulation Or Protocol: ASK, FSK, GFSK
• Data Rate - Maximum: 76.8 kbps
• Power - Output: -16dBm ~ 12dBm
• Current - Transmitting: 40mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

VOLTAGE CONTROLLED OSCILLATOR (VCO)
An on-chip VCO is included on the transmitter. The VCO
converts the control voltage generated by the loop filter into an
output frequency that is sent to the antenna via the power
amplifier (PA). The VCO has a typical gain of 80 MHz/V and
operates from 900 MHz–940 MHz. The PD1 bit in the function
register is the active high bit that turns on the VCO. A frequency
divide by 2 is included to allow operation in the lower 450 MHz
band. To enable operation in the lower band, the V1 bit in the
N Register should be set to 1.
The VCO needs an external 220 nF between the VCO and the
regulator to reduce internal noise.
RF OUTPUT STAGE
The RF output stage consists of a DAC with a number of current
sources to adjust the output power level. To set up the power level:
FSK GFSK: The output power is set using the modulation
register by entering a 7-bit number into the bits P1–P7. The two
MSBs set the range of the output stage, while the five LSBs set
the output power in the selected range.
ASK: The output power as set up for FSK is the output power
for a TxDATA of 1. The output power for a zero data bit is set
up the same way but using the bits D1–D7.
The output stage is powered down by setting bit PD2 in the
Function register to zero.
REV. 0
VCO CONTROL BIT
LOOP FILTER
C
REG
220nF
Figure 7. Voltage Controlled Oscillator
PIN
VCO
DIVIDE
BY 2
VCO SELECT BIT
MUX
TO PA AND
N DIVIDER
–17–
SERIAL INTERFACE
The serial interface allows the user to program the four 24-bit
registers using a 3-wire interface. (CLK, Data, and Load Enable).
The serial interface consists of a level shifter, 24-bit shift register,
and four latches. Signals should be CMOS compatible. The serial
interface is powered by the regulator, and therefore is inactive
when CE is low.
Data is clocked into the shift register, MSB first, on the rising edge
of each clock (CLK). Data is transferred to one of four latches on
the rising edge of LE. The destination latch is determined by the
value of the two control bits (C2 and C1). These are the two
LSBs, DB1 and DB0, as shown in the timing diagram of Figure 1.
P5
Figure 9. Output Stage Matching
PA
C2
0
0
1
1
Table I. C2, C1 Truth Table
Figure 8. Output Stage
V
P1
DD
C1
0
1
0
1
RF
OUT
Data Latch
R Register
N Register
Modulation Register
Function Register
L1
L2
HIGH
LOW
MED
C1
P7, P6
ADF7010
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