ADF7010BRUZ-REEL Analog Devices Inc, ADF7010BRUZ-REEL Datasheet - Page 18

• Manufacturer Part Number: ADF7010BRUZ-REEL
• Description: IC XMITTER ASK/FSK/GFSK 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of ADF7010BRUZ-REEL

• Frequency: 902MHz ~ 928MHz
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Modulation Or Protocol: ASK, FSK, GFSK
• Data Rate - Maximum: 76.8 kbps
• Power - Output: -16dBm ~ 12dBm
• Current - Transmitting: 40mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

ADF7010
FRACTIONAL-N
N COUNTER AND ERROR CORRECTION
The ADF7010 consists of a 15-bit sigma-delta fractional N
divider. The N Counter divides the output frequency to the output
stage back to the PFD frequency. It consists of a prescaler, integer,
and fractional part.
The prescaler can be 4/5 or 8/9. The spurious performance is
better with a 4/5 prescaler, and the N-value can be lower since
N
The output frequency of the PLL is:
Fractional-N Registers
The fractional part is made up of a 15-bit divide, made up of
a 12-bit N value in the N Register summed with a 10-bit (plus
sign bit) in the R-Register that is used for error correction, as
shown in Figure 12.
MIN
REFERENCE IN
is P
Figure 10. Output Impedance on Smith Chart
PFD Frequency
0.00
0.0
150
2
+ 3P + 3.
140
R
0.20
130
Figure 11. Fractional-N PLL
0.20
120
L(SHUNT) = 12nH
FRACTIONAL N
CHARGE
0.50
PUMP
PFD/
110
¥
0.50
Int
16 – j33
100
1.00
+
(
THIRD ORDER
- MODULATOR
90
1.00
2
3
L(SERIES) = 6.8nH
¥
80
Fractional
2.00
70
2
15
2.00
60
INTEGER N
5.00
50
)
VCO
5.00
+
N
40
Error
30
–18–
The resolution of each register is the smallest amount that the
output frequency can be changed by changing the LSB of the
register.
Changing the Output Frequency
The fractional part of the N Register changes the output fre-
quency by:
The frequency error correction contained in the R Register
changes the output frequency by:
By default, this will be set to 0. The user can calibrate the system
and set this by writing a twos complement number to Bits F1–F11
in the R Register. This can be used to compensate for initial error,
temperature drift, and aging effects in the crystal reference.
Integer N Register
The integer part of the N-Counter contains the prescaler and A and
B counters. It is eight bits wide and offers a divide of P
to 255.
The combination of the integer (255) and the fractional (31767/
31768) give a maximum N Divider of 256. The minimum PFD
usable is:
For use in the U.S. 902 MHz–928 MHz band, there is a restriction
to using a minimum PFD of 3.625 MHz to allow the user to have
a center frequency of 928 MHz.
PFD Frequency
The PFD frequency is the number of times a comparison is
made between the reference frequency and the feedback signal
from the output.
The higher the PFD frequency, the more often a comparison is
made at the PFD. This also allows a wider loop bandwidth
without compromising stability. This means that the frequency
lock time will be reduced when jumping from one frequency to
another by increasing the PFD.
M12 M11 M10
N14 N13 N12 N11 N10
F
PFD
(min)
(
F
Figure 12. Fractional Components
PFD
M9
)(
=
10-BIT (
M8
(
Frequency Error Correction Value
15-BIT FRACTIONAL N REGISTER
Maximum Output Frequency
F
PFD
F10
M7
N9
SIGN) ERROR CORRECTION
)(
12-BIT N VALUE
M6
N8
F9
N
-
Register Value
2
2
M5
F8
N7
12
15
(
255 1
M4
F7
N6
M3
N5
+
F6
)
M2
N4
F5
)
M1
F4
N3
Required
)
F3
N2
2
+ 3P + 3
REV. 0
F2
N1
F1
N0