RFPIC12F675F-I/SS Microchip Technology, RFPIC12F675F-I/SS Datasheet - Page 70

• Manufacturer Part Number: RFPIC12F675F-I/SS
• Description: IC MCU 1KX14 RF FSK/ASK 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of RFPIC12F675F-I/SS

• Package / Case: 20-SSOP
• Frequency: 380MHz ~ 450MHz
• Applications: RKE, Security Systems
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 40 kbps
• Power - Output: 10dBm
• Current - Transmitting: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1024 x 14 words Flash, 128 x 8 Byte EEPROM, 64 x 8 Byte SRAM
• Voltage - Supply: 2V ~ 5.5V
• Operating Temperature: -40°C ~ 125°C
• Processor Series: RFPIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DV164102, AC164101, AC164103
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 1.75 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164103 - MODULE RCVR RFPIC 433MHZAC164101 - MODULE TRANSMITTER RFPIC 433MHZDV164102 - KIT DEV RFPICKIT KIT 1AC124002 - MOD SKT PROMATEII 18SOIC/20SSOP
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3188156

rfPIC12F675
TABLE 10-8:
10.5
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt, (e.g., W register and
STATUS register). This must be implemented in
software.
Example 10-2 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x20 in Bank 0 and it must also be defined at 0xA0
in Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 10-2:
• Stores the W register
• Stores the STATUS register in Bank 0
• Executes the ISR code
• Restores the STATUS (and bank select bit
• Restores the W register
EXAMPLE 10-2:
DS70091A-page 68
0Bh, 8Bh INTCON
0Ch
8Ch
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
MOVWF
SWAPF
BCF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
Address
register)
:
:(ISR)
:
W_TEMP
STATUS,W
STATUS,RP0
STATUS_TEMP
STATUS_TEMP,W;swap STATUS_TEMP register into
STATUS
W_TEMP,F
W_TEMP,W
Context Saving During Interrupts
Shaded cells are not used by the Interrupt module.
PIR1
PIE1
Name
SUMMARY OF INTERRUPT REGISTERS
EEIE
;copy W to temp register,
;swap status to be saved into W
;change to bank 0 regardless of
;save status to bank 0 register
;move W into STATUS register
;swap W_TEMP
;swap W_TEMP into W
Bit 7
EEIF
GIE
SAVING THE STATUS AND
W REGISTERS IN RAM
could be in either bank
current bank
W, sets bank to original state
PEIE
ADIF
ADIE
Bit 6
Bit 5
T0IE
—
—
INTE
Bit 4
—
—
Preliminary
CMIF
CMIE
GPIE
Bit 3
10.6
The Watchdog Timer is a free running, on-chip RC
oscillator, which requires no external components. This
RC oscillator is separate from the external RC oscillator
of the CLKIN pin and INTOSC. That means that the
WDT will run, even if the clock on the OSC1 and OSC2
pins of the device has been stopped (for example, by
execution of a
operation, a WDT time-out generates a device RESET.
If the device is in SLEEP mode, a WDT time-out
causes the device to wake-up and continue with normal
operation. The WDT can be permanently disabled by
programming the configuration bit WDTE as clear
(Section 10.1).
10.6.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, V
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The
and the prescaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
10.6.2
It should also be taken in account that under worst case
conditions (i.e., V
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
Bit 2
T0IF
CLRWDT
—
—
DD
Watchdog Timer (WDT)
and process variations from part to part (see
WDT PERIOD
WDT PROGRAMMING
CONSIDERATIONS
Bit 1
INTF
—
—
and
SLEEP
DD
SLEEP
= Min., Temperature = Max., Max.
TMR1IF 00-- 0--0 00-- 0--0
TMR1IE 00-- 0--0 00-- 0--0
GPIF
Bit 0
 2003 Microchip Technology Inc.
instruction). During normal
instructions clear the WDT
0000 0000 0000 000u
POR, BOD
Value on
Value on all
RESETS
other