RFPIC12F675F-I/SS Microchip Technology, RFPIC12F675F-I/SS Datasheet - Page 76

IC MCU 1KX14 RF FSK/ASK 20SSOP

RFPIC12F675F-I/SS

Manufacturer Part Number
RFPIC12F675F-I/SS
Description
IC MCU 1KX14 RF FSK/ASK 20SSOP
Manufacturer
Microchip Technology
Series
PIC®r
Datasheets

Specifications of RFPIC12F675F-I/SS

Package / Case
20-SSOP
Frequency
380MHz ~ 450MHz
Applications
RKE, Security Systems
Modulation Or Protocol
ASK, FSK
Data Rate - Maximum
40 kbps
Power - Output
10dBm
Current - Transmitting
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
1024 x 14 words Flash, 128 x 8 Byte EEPROM, 64 x 8 Byte SRAM
Voltage - Supply
2V ~ 5.5V
Operating Temperature
-40°C ~ 125°C
Processor Series
RFPIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ICE2000, DV164102, AC164101, AC164103
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Program Memory Type
Flash
Program Memory Size
1.75 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164103 - MODULE RCVR RFPIC 433MHZAC164101 - MODULE TRANSMITTER RFPIC 433MHZDV164102 - KIT DEV RFPICKIT KIT 1AC124002 - MOD SKT PROMATEII 18SOIC/20SSOP
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3188156

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rfPIC12F675
TABLE 11-2:
DS70091A-page 74
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
BCF
BSF
BTFSC
BTFSS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF
Note:
Mnemonic,
Operands
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
assigned to the Timer0 module.
executed as a NOP.
Additional information on the mid-range instruction set is available in the PICmicro
Family Reference Manual (DS33023).
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f, b
f, b
f, b
f, b
k
k
k
k
k
k
k
k
k
-
-
-
-
-
-
f
f
rfPIC12F675 INSTRUCTION SET
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
BYTE-ORIENTED FILE REGISTER OPERATIONS
Description
BIT-ORIENTED FILE REGISTER OPERATIONS
LITERAL AND CONTROL OPERATIONS
Preliminary
Cycles
1 (2)
1 (2)
1(2)
1(2)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
1
2
2
2
1
1
1
GPIO
MSb
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
01
01
01
11
11
10
00
10
11
11
00
11
00
00
11
11
, 1), the value used will be that value present
14-Bit Opcode
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
00bb
01bb
10bb
11bb
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
bfff
bfff
bfff
bfff
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
 2003 Microchip Technology Inc.
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
LSb
Mid-Range MCU
Affected
C,DC,Z
C,DC,Z
C,DC,Z
C,DC,Z
Status
TO,PD
TO,PD
C
C
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Notes
1,2,3
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
2
3
3

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