SI4205-BM Silicon Laboratories Inc, SI4205-BM Datasheet - Page 9
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SI4205-BM
Manufacturer Part Number
SI4205-BM
Description
IC TXRX TRI-BAND 32LGA
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI4205-BM.pdf
(38 pages)
Specifications of SI4205-BM
Frequency
850MHz, 900MHz, 1.8GHz, 1.9GHz
Modulation Or Protocol
GSM
Applications
Cellular, GSM Cellular Radio
Voltage - Supply
2.7 V ~ 3.3 V
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Package / Case
32-LGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-
Operating Temperature
-
Sensitivity
-
Memory Size
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI4205-BM
Manufacturer:
SILICON
Quantity:
6 119
Company:
Part Number:
SI4205-BMR
Manufacturer:
SILAB
Quantity:
18 603
Table 5. Receiver Characteristics (Continued)
(V
Parameter
Analog PGA Control Range
Analog PGA Step Size
Digital PGA Control Range
Digital PGA Step Size
Maximum Differential Output Voltage
Output Common Mode Voltage
Differential Output Offset Voltage
Differential Output Offset Voltage Drift
Baseband Gain Error
Baseband Phase Error
Output Load Resistance
Output Load Capacitance
Group Delay
Differential Group Delay
Powerup Settling Time
Notes:
DD
1. GSM input pins RFIGP and RFIGN. DCS input pins RFIDP and RFIDN. PCS input pins RFIPP and RFIPN.
2. Measurement is performed with a 2:1 balun (50 Ω input, 200 Ω balanced output) and includes matching network and
3. Specifications guaranteed by characterization using LQW15AN series matching inductors.
4. Input signal at balun is –102 dBm. SNR at baseband output is 9 dB.
5. AGAIN[2:0]=min=000
6. AGAIN[2:0]=min=000
7. Voltage gain is defined as the differential rms voltage at the RXIP/RXIN pins or RXQP/RXQN pins divided by the rms
8. Voltage gain is defined as the differential rms voltage at the LNA output divided by the rms voltage at the balun output.
9. Output pins RXIP, RXIN, RXQP, RXQN.
10. Specified as root sum square:
11. The baseband signal path is entirely digital. Gain, phase, and offset errors at the baseband outputs are because of the
12. Group delay is measured from antenna input to baseband outputs. Differential group delay is measured in-band.
13. Includes settling time of the frequency synthesizer. Settling to 5 degrees phase error measured at RXIP, RXIN, RXQP,
= 2.7 to 3.0 V, T
PCB losses. Measured at max gain (AGAIN[2:0] =100
Noise figure measurements are referred to 290 °K. Insertion loss of the balun is removed.
voltage at the balun input with DACFS[1:0] = 01 and CSEL = 1. Gain is 1.5 dB higher with CSEL = 0. Minimum and
maximum values do not include the variation in the DAC full scale voltage (also see Maximum Differential Output
Voltage specification).
calibration and is guaranteed by characterization. See ZERODEL[2:0] in the register description.
D/A converters. Offsets can be measured and calibrated out. See ZERODEL[2:0] in the register description.
and RXQN pins.
12
A
= –20 to 85 °C)
9,11
3,13
9,11
12
9
9
b
b
, LNAG[1:0] = max=01
, LNAG[1:0] = min=00
9
9,10,11
(
RXIP RXIN
9
9,10,11
–
Symbol
∆G
∆G
b
b
, LNAC[1:0] = min=00
R
C
APGA
DPGA
, LNAC[1:0] =max= 01
)
L
L
2
+
(
Rev. 1.0
RXQP RXQN
b
, LNAG[1:0] = 01
DACCM[1:0] = 00
DACCM[1:0] = 01
DACCM[1:0] = 10
From powerdown
DACFS[1:0] = 00
DACFS[1:0] = 01
DACFS[1:0] = 10
Test Condition
Single-ended
Single-ended
CSEL = 0
CSEL = 1
CSEL = 0
CSEL = 1
–
b
.
b
)
.
2
. Drift specification applies to dc offset
b
, LNAC[1:0] = 01
1.05
1.15
Min
3.2
0.7
1.5
2.6
0.8
13
10
—
—
—
—
—
—
—
—
—
—
—
—
b
) unless otherwise noted.
1.25
1.35
Typ
200
4.0
1.0
2.0
3.5
1.0
16
63
—
—
—
—
—
—
—
—
—
—
1
1.45
1.55
Max
220
4.8
1.3
2.5
4.4
1.2
1.5
19
16
10
22
16
—
—
—
5
1
1
1
Aero I
V
V
V
Unit
deg
mV
mV
dB
dB
dB
dB
kΩ
pF
µs
µs
µs
µs
µs
PPD
PPD
PPD
%
V
V
V
9