SI4205-BM Silicon Laboratories Inc, SI4205-BM Datasheet - Page 19
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SI4205-BM
Manufacturer Part Number
SI4205-BM
Description
IC TXRX TRI-BAND 32LGA
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI4205-BM.pdf
(38 pages)
Specifications of SI4205-BM
Frequency
850MHz, 900MHz, 1.8GHz, 1.9GHz
Modulation Or Protocol
GSM
Applications
Cellular, GSM Cellular Radio
Voltage - Supply
2.7 V ~ 3.3 V
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Package / Case
32-LGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-
Operating Temperature
-
Sensitivity
-
Memory Size
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI4205-BM
Manufacturer:
SILICON
Quantity:
6 119
Company:
Part Number:
SI4205-BMR
Manufacturer:
SILAB
Quantity:
18 603
Frequency Synthesizer
The Aero I transceiver integrates two complete PLLs
including VCOs, varactors, resonators, loop filters,
reference and VCO dividers, and phase detectors. The
RF PLL uses two multiplexed VCOs. The RF1 VCO is
used for receive mode, and the RF2 VCO is used for
transmit mode. The IF PLL is used only during transmit
mode. All VCO tuning inductors are also integrated.
The IF and RF output frequencies are set by
programming the N-Divider registers, N
N
or RF2 automatically selects the proper VCO. The
output frequency of each PLL is as follows:
The DIV2 bit in register 31h controls a programmable
divider at the XIN pin to allow either a 13 or 26 MHz
reference frequency. For receive mode, the RF1 PLL
phase detector update rate (f
f
f
transmit mode, the RF2 and IF PLL phase detector
update rates are always f
φ
φ
IF
= 100 kHz for DCS 1800 or PCS 1900 bands, and
= 200 kHz for GSM 850 and E-GSM 900 bands. For
. Programming the N-Divider register for either RF1
SCLK
XOUT
SDO
XEN
PDN
SEN
SDI
XIN
Control
Power
Serial
f
OUT
I/O
φ
DIV2
=
=200 kHz.
1, 2
Figure 11. Frequency Synthesizer Block Diagram
SDOSEL[4:0]
N f
φ
PDIB
PDRB
) should be programmed
×
φ
RFUP
130
65,
RF1
, N
Tune
Tune
DET
Self
Self
DET
RF2
and
Rev. 1.0
RF PLL
IF PLL
N
N
N
RF1
RF2
IF
[15:0]
RF1
RF2
[15:0]
[15:0]
N
N
Si4205
To
RX/TX
To TX
Aero I
19