ATR2434-PLT Atmel, ATR2434-PLT Datasheet
ATR2434-PLT
Specifications of ATR2434-PLT
Related parts for ATR2434-PLT
ATR2434-PLT Summary of contents
Page 1
... Consumer Electronics – Barcode Scanners – POS Peripherals – Toys Functional Description The ATR2434 transceiver is a single-chip 2.4-GHz Direct Sequence Spread Spectrum (DSSS) Gaussian Frequency Shift Keying (GFSK) baseband modem radio that con- nects directly to a microcontroller. ™ WirelessUSB 2.4-GHz DSSS ...
Page 2
... Figure 1. Simplified Block Diagram ita Pin Configuration Figure 2. Pinning QFN48 RFOUT VCC NC NC VCC ATR2434 [Preliminary nthe s ize ATR2434 X13IN 34 PACTL VCC VCC 28 VCC X13OUT 25 SCK 4822D–ISM–10/04 ...
Page 3
... IRQ. Interrupt and SERDES bypass mode DIOCLK. N/A Master-output-slave-input data. SPI data input pin. Hi-Z Master-input-slave-output data. SPI data output pin. N/A SPI input clock. SPI clock. N/A Slave select enable. SPI enable. H VCC = 2 3 Ground = 0 V. N/A Tie to ground. L Must be tied to ground. ATR2434 [Preliminary] 3 ...
Page 4
... ETSI EN 301 489-1 V1.4.1, ETSI EN 300 328-1 V1.3.1 (European Countries); FCC CFR 47 Part 15 (USA and Industry Canada) and ARIB STD-T66 (Japan). The ATR2434 contains a 2.4-GHz radio transceiver, a GFSK modem and a dual DSSS reconfigurable baseband. The radio and baseband are both code- and frequency-agile. ...
Page 5
... The ATR2434 has a programmable trim capability for adjusting the on-chip load capacitance supplied to the crystal. The Radio Frequency (RF) circuitry has on- chip decoupling capacitors. The ATR2434 is powered from supply. The ATR2434 can be shutdown to a fully static state using the PD pin. ...
Page 6
... A RSSI register value greater than 28 indicates the presence of a strong signal. The ATR2434 has a four-wire SPI communication interface between an application MCU and one or more slave devices. The SPI interface supports single-byte and multi- byte serial transfers. The four-wire SPI communications interface consists of Master Out-Slave In (MOSI), Master In-Slave Out (MISO), Serial Clock (SCK), and Slave Select (SS) ...
Page 7
... Figure 3 and Figure 4, respectively. The SPI communications interface single write and burst write sequences are shown in Figure 5 and Figure 6 on page 8, respectively. Table 1. SPI Transaction Format Byte 1 Bit # 7 Bit Name DIR addr data from ATR2434 [Preliminary] Byte [5:0] INC Address [7:0] Data 7 ...
Page 8
... IRQ DIOVAL DIO Figure 8. DIO Transmit Sequence IRQ DIOVAL v0 v1 DIO d0 d1 ATR2434 [Preliminary fro The DIO communications interface is an optional SERDES bypass data-only transfer interface. In receive mode, DIO and DIOVAL are valid after the falling edge of IRQ, which clocks the data as shown in Figure 7. In transmit mode, DIO and DIOVAL are sampled on the falling edge of the IRQ, which clocks the data as shown in Figure 8 ...
Page 9
... Transmit Interrupts Receive Interrupts 4822D–ISM–10/04 The ATR2434 features three sets of interrupts: transmit, receive, and a wake interrupt. These interrupts all share a single pin (IRQ), but can be independently enabled/ disabled. In transmit mode, all receive interrupts are automatically disabled, and in transmit mode all receive interrupts are automatically disabled. However, the contents of the enable registers are preserved when switching between transmit and receive modes ...
Page 10
... Synthesizer Lock Count Manufacturing ID Note: 1. All registers are accessed Little Endian. ATR2434 [Preliminary] 10 Table 2 displays the list of registers inside the ATR2434 that are addressable through the SPI interface. All registers are read and writable, except where noted. Mnemonic REG_ID REG_SYN_A_CNT REG_SYN_N_CNT ...
Page 11
... N registers is done through the Channel register (Reg 0x21, bit 7). When in Channel mode the A and N Count bits can be used to read the A and N values derived directly from the Channel. 4822D–ISM–10/04 REG_ID REG_SYN_A_CNT REG_SYN_N_CNT Count ATR2434 [Preliminary] Default: 0x07 2 1 Product ID Default: 0x00 2 1 Count Default: 0x00 ...
Page 12
... Syn Enable The Synthesizer Enable bit is used to enable or disable the Synthesizer Synthesizer Enabled 0 = Synthesizer Disabled This bit only applies when Auto Syn Disable bit is selected (Reg 0x03, bit 1 = 1), otherwise this bit is do not care. ATR2434 [Preliminary] 12 REG_CONTROL Code Auto Syn ...
Page 13
... PN codes. Note: 1. The following Reg 0x04, bits 2:0 values are not valid: · 001-Not Valid · 010-Not Valid · 011-Not Valid · 111-Not Valid 4822D–ISM–10/04 REG_DATA_RATE 5 4 Reserved ATR2434 [Preliminary] Default: 0x00 Code Width Data Rate 0 Sample Rate 13 ...
Page 14
... The EOF event causes data to be moved to the proper SERDES Data Register and can also be used to generate interrupts the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. Table 10. Receive Interrupt Enable Addr: 0x07 7 6 Underflow B Overflow B ATR2434 [Preliminary] 14 REG_CONFIG Receive Transmit Invert ...
Page 15
... A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. 4822D–ISM–10/04 ATR2434 [Preliminary] 15 ...
Page 16
... Overflow conditions occur when the radio loads new data into the Receive SERDES Data A register (Reg 0x09) before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data A register (Reg 0x09) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08) ATR2434 [Preliminary] 16 REG_RX_INT_STAT 5 ...
Page 17
... Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only. 4822D–ISM–10/04 REG_RX_DATA_A Data REG_RX_VALID_A Valid REG_RX_DATA_B Data ATR2434 [Preliminary] Default: 0x00 2 1 Default: 0x00 2 1 Default: 0x00 ...
Page 18
... The Empty bit is used to enable the interrupt that signals when the Transmit SERDES register (Reg 0x0F) is empty Empty interrupt enabled 0 = Empty interrupt disabled The Empty condition occurs when the Transmit SERDES Data register (Reg 0x0F) is loaded into the transmit buffer and it's safe to load the next byte ATR2434 [Preliminary] 18 REG_RX_VALID_B ...
Page 19
... IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These registers are read-only. 4822D–ISM–10/04 REG_TX_INT_STAT Underflow ATR2434 [Preliminary] Default: 0x00 2 1 Overflow Done 0 Empty ...
Page 20
... PN codes and these can be used alone or with each other to accomplish faster data rates. Not any 64 chips/bit value can be used code as there are certain characteristics that are needed to minimize the possibility of multiple PN codes interfering with each other or the possibility of invalid correlation. The over-the-air order is bit 0 followed by bit 1, followed by bit 62, followed by bit 63. ATR2434 [Preliminary] 20 REG_TX_DATA 5 ...
Page 21
... On the other hand increasing the maximum number of missed chips means reduced data integrity but increased robustness to interference and increased range. 4822D–ISM–10/04 REG_THRESHOLD_L Threshold Low REG_THRESHOLD_H Threshold High ATR2434 [Preliminary] Default: 0x08 2 1 Default: 0x38 ...
Page 22
... These bits are reserved. This register is read-only. 0 Wake-up Wake-up status. Status 0 = Wake interrupt not pending 1 = Wake interrupt pending This IRQ will assert when a wake-up condition occurs. This bit is cleared by reading the Wake Status register (Reg 0x1D). This register is read-only. ATR2434 [Preliminary] 22 REG_WAKE_EN Reserved REG_WAKE_STAT 5 ...
Page 23
... GHz, while a value of 79 corresponds to a frequency of 2.479 GHz. The channels are separated from each other by 1 MHz intervals. 4822D–ISM–10/04 REG_ANALOG_CTL 5 4 MID Read Reserved Reserved Enable REG_CHANNEL 5 4 Channel ATR2434 [Preliminary] Default: 0x00 Output PaInv Enable Default: 0x00 Rst ...
Page 24
... The Crystal Adjust value is used to calibrate the on-chip load capacitance supplied to the crystal. The Crystal Adjust value will depend on the parameters of the crystal being used. Refer to the appropriate reference material for information about choosing the optimum Crystal Adjust value. ATR2434 [Preliminary] 24 REG_RSSI ...
Page 25
... When set, this bit overrides the carrier detect. The user must set Reg 20, bit enable writes to Override Reg 0x2F. 6:0 Reserved These bits are reserved and should be written with zeros. 4822D–ISM–10/04 REG_VCO_CAL REG_AGC_CTL Reserved REG_CARRIER_DETECT Reserved ATR2434 [Preliminary] Default: 0x00 2 1 Reserved Default: 0x00 2 1 Default: 0x00 ...
Page 26
... MID Read Enable bit (bit 5) is set in the Analog Control register (Reg 0x20). Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. The MID Read Enable bit in the Analog Control register (Reg 0x20, bit 5) should only be set when reading the contents of the Manufacturing ID register (Reg 0x3C to 0x3F). This register is read-only. ATR2434 [Preliminary] 26 REG_CLOCK_MANUAL 5 ...
Page 27
... Human Body Model (HBM). Operating Conditions Parameters Supply voltage Ambient temperature under bias Ground voltage Oscillator or crystal frequency) 4822D–ISM–10/04 ATR2434 [Preliminary] Pin Symbol -65 to +150 -55 to +125 -0.3 to +3 inputs through a series resistor limiting input current to 1 mA. ...
Page 28
... It is permissible to connect voltages above V 3. Average I when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the WirelessUSB CC 1-way protocol. 4. Average I when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the WirelessUSB CC 2-way protocol. ATR2434 [Preliminary] 28 Symbol -100.0 µ OH1 = -2 ...
Page 29
... SCK HI pulse for SPI burst reads only fro ata K_CYC t t SCK _LO SC K_HI (BU RST R EAD) th every 9 SC K_H I data to mcu t D AT_VAL ATR2434 [Preliminary] Min. Typ. 476 (2) 238 158 158 10 (3) 97 (3) 77 250 ata fro ata every 10 SC K_HI data to mcu Max. Unit ...
Page 30
... Minimum IRQ high time - 32 chips/bit RX_IRQ_HI Minimum IRQ high time - 64 chips/bit Minimum IRQ low time - 32 chips/bit DDR t Minimum IRQ low time - 32 chips/bit RX_IRQ_LO Minimum IRQ low time - 64 chips/bit Figure 11. DIO Receive Timing Diagram IRQ DIO/ DIOVAl ATR2434 [Preliminary RX_IRQ_HI RX_IRQ_LO data t RX_DIO_VLD t RX_DIOVAL_VLD Min. ...
Page 31
... TX_DIO_SU t TX_DIOVAL_SU Conditions ( -60 dBm C = -60 dBm C = -60 dBm C = -67 dBm C = -67 dBm C = -67 dBm ( -67 dBm (3) N ±1 MHz -67 dBm C = -64 dBm f = 5,10 MHz = 13.000 MHz Seven steps, monotonic ATR2434 [Preliminary] data t TX_DIO_HLD t TX_DIOVAL_HLD Min. Typ. 2.400 -85 -20 - -30 -40 -20 -25 -30 -20 -39 ...
Page 32
... Figure 14 illustrates default values for the Configuration register (Reg 0x05, bits 1:0 wake-up event is triggered when the PD pin is deasserted. Figure 14 illustrates a wake-up event configured to trigger an IRQ pin event via the Wake Enable register (Reg 0x1C, bit 0 = 1). ATR2434 [Preliminary] 32 Conditions PN code pattern 10101010 ...
Page 33
... R2 937 R 500 3.00 CC 4822D–ISM–10/ I_R _IN T OUTPUT 5 pF INCLUDING JIG AND SCOPE Typical V Unit CC GND Rise time: 1 V/ns V Equivalent to: V OUTPUT ATR2434 [Preliminary Test Load OUTPUT R2 ALL INPUT PULSES 90% 90% 10% 10% Fall time: 1 V/ns VENIN EQUIVALENT THÉ ...
Page 34
... Ordering Information Extended Type Number ATR2434-PLT ATR2434-PLT Package Information ATR2434 [Preliminary] 34 Package Remarks QFN48 - 7x7 Tray QFN48 - 7x7 Samples 4822D–ISM–10/04 ...
Page 35
... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...