AT86RF211SAHW E2V, AT86RF211SAHW Datasheet - Page 27

• Manufacturer Part Number: AT86RF211SAHW
• Description: IC RF TXRX FSK 400-950MHZ 48TQFP
• Manufacturer: E2V

Specifications of AT86RF211SAHW

• Frequency: 400MHz ~ 950MHz
• Data Rate - Maximum: 100kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 7dBm ~ 12dBm
• Sensitivity: -107dBm
• Voltage - Supply: 2.4 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Current - Transmitting: -
• Current - Receiving: -

4.4
4.4.1
4.4.1.1
4.4.1.2
e2v semiconductors SAS 2008
Digital Features
Clock Recovery Function
Preamble
Algorithm Overview
The clock recovery algorithm in the AT86RF211S has been improved and the new algorithm must be
used. To use the new algorithm:
For compatibility purposes only, it is nevertheless possible to run the former algorithm, (the algorithm of
the AT86RF211). This algorithm is automatically activated in the RF211 mode or if bit NEWDATACLK is
kept in reset state in RF211S mode.
It is now possible, in RF211S mode only, to inhibit the clock recovery when RSSI is too low, leaving the
MCU in sleep mode. This is performed by the DATACLKEN bit in the DTR register.
The clock recovery function is activated by setting the DATACLK bit of the CTRL1 register to 1.
The clock recovery function provides the data clock on the DATACLK pin, synchronized on the received
data flow. The targeted position for the rising edge of the clock is the middle of the data bit, eliminating
synchronization problems and facilitating readout by the microcontroller.
The clock’s recovery mechanism is based on the generation of a basic data clock with a period given by
the DATARATE of CTRL2 with a step of approximately 100 ns. This basic clock is synchronized on the
received data flow. The phase correction step is fixed by DATATOL of the CTRL2 register (steps of
approximately 100 ns also).
Therefore, DATATOL can:
The best DATATOL value is a a balance of the above three points.
The synchronization mechanism is explained by the chronogram in
for the first bit. In worst case scenarios, when the data and clock arrive at the same time, synchronization
begins at the second bit. Notice that the DATACLK signal is available as soon as the DATACLK bit is
programmed, regardless of the state of the DATAMSG pin.
The programmed data rate enables the creation of a basic clock at the programmed DATARATE fre-
quency at the beginning of reception. The clock is then shifted if necessary from the tolerance value,
1. Put the device into RF211S mode: ADDFEAT = CTRL1[0] = 1
2. Select the improved algorithm by setting bit NEWDATACLK = DTR[13] = 1
• Compensate for the difference between the read data rates from the transmitter and the receiver
• Allow fast initial synchronization of the data clock, avoiding bit transition times, and converge towards
• Keep the appropriate data rate (no additional and no removed bit) when noisy data with a bad bit
(fixed by DATARATE).
the middle of the bit.
transition position arrives.
– If the tolerance is too high, the rate value is reached earlier, and could be unstable (too big a
– If the tolerance is too low, it could be difficult to catch up with the data and the function may
– The tolerance is able to compensate for the difference of datarate generators between Rx
step).
be lost.
and Tx.
Figure
4-26. Synchronization is done
0894C–WIRE–11/08
AT86RF211S
27