ATMEGA2560R231-AU Atmel, ATMEGA2560R231-AU Datasheet - Page 350
ATMEGA2560R231-AU
Manufacturer Part Number
ATMEGA2560R231-AU
Description
BUNDLE ATMEGA2560/RF231 TQFP
Manufacturer
Atmel
Datasheet
1.ATMEGA640V-8CU.pdf
(444 pages)
Specifications of ATMEGA2560R231-AU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
100-TFBGA
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
256 KB
Data Ram Size
8 KB
Development Tools By Supplier
ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Power - Output
-
Operating Temperature
-
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
Details
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29.8.1
29.8.2
2549M–AVR–09/10
Serial Programming Pin Mapping
Serial Programming Algorithm
Table 29-15. Pin Mapping Serial Programming
Figure 29-10. Serial Programming and Verify
Notes:
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the ATmega640/1280/1281/2560/2561, data is clocked on the rising
edge of SCK.
When reading data from the ATmega640/1280/1281/2560/2561, data is clocked on the falling
edge of SCK. See
Symbol
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
PDO
SCK
PDI
XTAL1 pin.
programming the EEPROM, an auto-erase cycle is built into the self-timed programming oper-
ation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
CC
- 0.3V < AVCC < V
Figure 29-12 on page 353
(TQFP-100)
Pins
PB2
PB3
PB1
PDO
SCK
PDI
ck
ck
CC
ATmega640/1280/1281/2560/2561
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8V - 5.5V.When
XT AL1
RESET
GND
(TQFP-64)
for timing details.
(1)
Pins
PE0
PE1
PB1
AVCC
VCC
+1.8V - 5.5V
+1.8V - 5.5V
I/O
O
I
I
(2)
ck
ck
>= 12 MHz
>= 12 MHz
Serial Data out
Serial Data in
Description
Serial Clock
350
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