ATMEGA2560R231-AU Atmel, ATMEGA2560R231-AU Datasheet - Page 157
ATMEGA2560R231-AU
Manufacturer Part Number
ATMEGA2560R231-AU
Description
BUNDLE ATMEGA2560/RF231 TQFP
Manufacturer
Atmel
Datasheet
1.ATMEGA640V-8CU.pdf
(444 pages)
Specifications of ATMEGA2560R231-AU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
100-TFBGA
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
256 KB
Data Ram Size
8 KB
Development Tools By Supplier
ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Power - Output
-
Operating Temperature
-
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
Details
- Current page: 157 of 444
- Download datasheet (10Mb)
2549M–AVR–09/10
Figure 16-12
frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
The same renaming applies for modes that set the TOVn Flag at BOTTOM.
Figure 16-12. Timer/Counter Timing Diagram, no Prescaling
Figure 16-13
Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (f
(PC and PFC PWM)
and ICF n
and ICFn
(CTC and FPWM)
TOVn
(Update at TOP)
(PC and PFC PWM)
TOVn
(CTC and FPWM)
(Update at TOP)
TCNTn
TCNTn
OCRnx
as TOP)
(clk
TCNTn
TCNTn
OCRnx
(clk
as TOP)
clk
clk
clk
clk
I/O
I/O
shows the count sequence close to TOP in various modes. When using phase and
shows the same timing data, but with the prescaler enabled.
(FPWM)
(FPWM)
I/O
Tn
I/O
Tn
/8)
/1)
(if used
(if used
TOP - 1
TOP - 1
TOP - 1
TOP - 1
Old OCRnx Value
ATmega640/1280/1281/2560/2561
Old OCRnx Value
TOP
TOP
TOP
TOP
BOTTOM
BOTTOM
TOP - 1
TOP - 1
clk_I/O
New OCRnx Value
New OCRnx Value
/8)
BOTTOM + 1
BOTTOM + 1
TOP - 2
TOP - 2
157
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