ATMEGA2560R231-AU Atmel, ATMEGA2560R231-AU Datasheet - Page 195
ATMEGA2560R231-AU
Manufacturer Part Number
ATMEGA2560R231-AU
Description
BUNDLE ATMEGA2560/RF231 TQFP
Manufacturer
Atmel
Datasheet
1.ATMEGA640V-8CU.pdf
(444 pages)
Specifications of ATMEGA2560R231-AU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
100-TFBGA
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
256 KB
Data Ram Size
8 KB
Development Tools By Supplier
ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Power - Output
-
Operating Temperature
-
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (10Mb)
20. SPI – Serial Peripheral Interface
2549M–AVR–09/10
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega640/1280/1281/2560/2561 and peripheral devices or between several AVR devices.
The ATmega640/1280/1281/2560/2561 SPI includes the following features:
•
•
•
•
•
•
•
•
USART can also be used in Master SPI mode, see
The Power Reduction SPI bit, PRSPI, in
page 50 must be written to zero to enable SPI module.
Figure 20-1. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in
196. The system consists of two shift Registers, and a Master clock generator. The SPI Master
initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave.
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
1. Refer to
/2/4/8/16/32/64/128
DIVIDER
Figure 1-1 on page
ATmega640/1280/1281/2560/2561
(1)
2, and
“PRR0 – Power Reduction Register 0” on page 56
Table 12-6 on page 79
“USART in SPI Mode” on page
for SPI pin placement.
Figure 20-2 on page
232.
195
on
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