ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 415
ATMEGA128RFA1-ZUR
Manufacturer Part Number
ATMEGA128RFA1-ZUR
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
Specifications of ATMEGA128RFA1-ZUR
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
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27.5.2 Start-Up Timing
8266B-MCU Wireless-03/11
Figure 27-3. ADC Prescaler
The ADC module contains a prescaler, which generates an acceptable ADC clock
frequency from any CPU frequency above 100 kHz. The pre-scaling is set by the ADPS
bits in ADCSRA. The prescaler starts counting from the moment when the ADC is
enabled. The prescaler keeps running for as long as the ADEN bit is set, and is
continuously reset when ADEN is low.
The ADC is enabled by setting the ADEN bit in ADCSRA. First the analog voltage
regulator is powered up which takes t
Characteristics" on page
ADCSRB.
After AVDD has stabilized, the ADC is started. The ADC start-up time has a length of
t
differential input channels are used, then an additional initialization period t
required by the gain amplifier. This period is configured by the Track-And-Hold Time
bits, ADTHT1:0 in ADCSRC. ADSUT4:0 and ADTHT1:0 are fixed numbers of ADC
clock cycles and can be setup for different ADC clock speeds.
The minimum required ADC start-up time is 20 µs. Note that for the maximum ADC
speed of 8 MHz the start-up time can not be set higher than 16 µs in ADSUT4:0. Under
this condition the user has either to ensure that a conversion is not started earlier than
20 µs after the ADC is enabled or the first conversion result should be discarded.
For a summary of start-up times and sequences see
below,
Table 27-1. Start-Up Time, Single Ended Channels
Table 27-2. Start-Up Time, Differential Channels
ADSU
Parameter
ADC Start-Up Time t
Parameter
ADC Start-Up Time t
Gain Amplifier Initialization Time t
and can be adjusted by the Start-Up time bits ADSUT4:0 in ADCSRC. If
Figure 27-4 on
ADEN
START
ADSU
ADSU
page 416 and
ADPS0
ADPS1
ADPS2
CK
506). A stable AVDD is indicated by the AVDDOK bit in
AINIT
Figure 27-5 on
Reset
AVREG
7-BIT ADC PRESCALER
Duration in ADC Clock Cycles
4(ADSUT+1), minimum 20 µs
Duration in ADC Clock Cycles
4(ADSUT+1), minimum 20 µs
2(ADTHT+2)
ADC CLOCK SOURCE
(see
page 416.
ATmega128RFA1
"Power Management Electrical
Table 27-1
below,
Table 27-2
AINIT
415
is
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