ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 195
ATMEGA128RFA1-ZUR
Manufacturer Part Number
ATMEGA128RFA1-ZUR
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
Specifications of ATMEGA128RFA1-ZUR
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
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8266B-MCU Wireless-03/11
PCINT4, Pin Change Interrupt source 4: The PB4 pin can serve as an external interrupt
source.
• MISO/PDO/PCINT3 – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is
enabled as a master, this pin is configured as an input regardless of the setting of
DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by
DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB3 bit.
PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this
pin is used as data output line (see section
details).
PCINT3, Pin Change Interrupt source 3: The PB3 pin can serve as an external interrupt
source.
• MOSI/PDI/PCINT2 – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB2.
When the SPI is enabled as a master, the data direction of this pin is controlled by
DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB2 bit.
PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin
is used as data input line (see section
PCINT2, Pin Change Interrupt source 2: The PB2 pin can serve as an external interrupt
source.
• SCK/PCINT1 – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is
enabled as a slave, this pin is configured as an input regardless of the setting of DDB1.
When the SPI0 is enabled as a master, the data direction of this pin is controlled by
DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the
PORTB1 bit.
PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt
source.
• SS
SS
as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this
pin is driven low. When the SPI is enabled as a master, the data direction of this pin is
controlled by DDB0. When the pin is forced to be an input, the pull-up can still be
controlled by the PORTB0 bit.
Table 14-4 below
the overriding signals shown in
SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR
OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt
source.
Table 14-4. Overriding Signals for Alternate Functions in PB7:PB4
Signal
Name
¯ ¯ : Slave Port Select input. When the SPI is enabled as a slave, this pin is configured
PUOE
¯ ¯ /PCINT0 – Port B, Bit 0
PB7/OC0A/OC1C
0
and
Table 14-5 on
PB6/OC1B
0
Figure 14-5 on
page 196 relate the alternate functions of Port B to
"Serial Downloading" on page 478
"Serial Downloading" on page 478
page 192. SPI MSTR INPUT and SPI
PB5/OC1A
0
ATmega128RFA1
PB4/OC2A
0
for details).
195
for
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