ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 162
ATMEGA128RFA1-ZUR
Manufacturer Part Number
ATMEGA128RFA1-ZUR
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA128-16AU.pdf
(385 pages)
2.ATAVR128RFA1-EK1.pdf
(13 pages)
3.ATAVR128RFA1-EK1.pdf
(555 pages)
Specifications of ATMEGA128RFA1-ZUR
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
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12.5 Supply Voltage and Leakage Control
12.5.1 Power-chain
Figure 12-1. Power-chain connections
162
ATmega128RFA1
The radio transceiver has a separate reset signal. A radio transceiver reset is initiated
by setting bit TRXRST in register TRXPR. This bit is self-resetting.
The radio transceiver signal SLPTR can be controlled by the bit SLPTR in register
TRXPR and is used to set the radio transceiver into SLEEP mode (assuming
TRX_STATE is TRX_OFF). This bit has a multiple function, see section
GHz Transceiver" on page 30
For battery applications using DEEP_SLEEP periods, the leakage current defines the
system life time. Due to the typical strong temperature dependency of the leakage
current, major contributors to the leakage budget are turned off:
• Analog and digital voltage regulator,
• Non-volatile memory (NVM),
• SRAM,
• Digital signal processor of the radio transceiver including AES engine.
If the CPU uses one of the sleep modes “power-down” or “power-save”, the above
mentioned blocks will be switched off by power switches. When the CPU wakes up, the
blocks are switched on again. There are some additional exceptions (internal voltage
regulator, SRAM, radio transceiver), see section
The supply voltage control is mainly hidden to the application, it is not necessary to
configure the supply voltage control. Nevertheless some configurations can be done in
order to get the maximum effect and the lowest sleep current, for details see section
"SRAM with Data Retention" on
The following figure shows the major dependencies of the power-chain and how the
power switches are situated inside the chain.
Startup and Wakeup from DEEP_SLEEP
After power-on reset (POR) or wakeup from DEEP_SLEEP the power switches of the
blocks will be enabled one after another (power-chained) to decrease current peaks.
The blocks will be enabled in the following order:
1. Bandgap reference and voltage regulator,
2. Digital voltage regulator (DVREG) and low leakage voltage regulator (LLVREG),
for a detailed description of the radio transceiver.
page 164.
"Power-chain" below
8266B-MCU Wireless-03/11
.
"Low-Power 2.4
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