AT86RF231-ZFR Atmel, AT86RF231-ZFR Datasheet - Page 101
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AT86RF231-ZFR
Manufacturer Part Number
AT86RF231-ZFR
Description
TXRX LOW POWER 2.4GHZ 32VQFN
Manufacturer
Atmel
Datasheet
1.AT86RF231-ZUR.pdf
(198 pages)
Specifications of AT86RF231-ZFR
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
Applications
Industrial Monitoring and Control, Wireless Alarm and Security Systems
Power - Output
-17dBm ~ 3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.3mA
Current - Transmitting
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
2405 MHz to 2480 MHz
Interface Type
SPI
Noise Figure
6 dB
Output Power
20 dB
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
12.3 mA
Minimum Operating Temperature
- 40 C
Modulation
OQPSK
Protocol Supported
802.15.4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
AT86RF231-ZFR
AT86RF231-ZFRTR
AT86RF231-ZFRTR
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9. Module Description
9.1
9.1.1
8111C–MCU Wireless–09/09
Receiver (RX)
Overview
The AT86RF231 receiver is split into an analog radio front end and a digital base band proces-
sor (RX BBP), see
Figure 9-1.
The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) and down
converted to an intermediate frequency by a mixer. Channel selectivity is performed using an
integrated band pass filter (BPF). A limiting amplifier (Limiter) provides sufficient gain to over-
come the DC offset of the succeeding analog-to-digital converter (ADC) and generates a digital
RSSI signal. The ADC output signal is sampled and processed further by the digital base band
receiver (RX BBP).
The RX BBP performs additional signal filtering and signal synchronization. The frequency offset
of each frame is calculated by the synchronization unit and is used during the remaining receive
process to correct the offset. The receiver is designed to handle frequency and symbol rate devi-
ations up to ±120 ppm, caused by combined receiver and transmitter deviations. For details
refer to
nal is demodulated and the data are stored in the Frame Buffer.
In Basic Operating Mode, refer to
of a frame is indicated by an interrupt IRQ_2 (RX_START). Accordingly its end is signalized by
an interrupt IRQ_3 (TRX_END). Based on the quality of the received signal a link quality indica-
tor (LQI) is calculated and appended to the frame, refer to
(LQI)” on page
status information like ED value (register 0x07, ED_LEVEL) and FCS correctness (register
0x06, PHY_RSSI).
Beyond these features the Extended Operating Mode of the AT86RF231 supports address filter-
ing and pending data indication. For details refer to
page
RFP
RFN
47.
Section 12.5 “General RF Specifications” on page 158
LNA
Receiver Block Diagram
99. Additional signal processing is applied to the frame data to provide further
Figure 9-1 on page
PPF
LO
Section 7.1 “Basic Operating Mode” on page
BPF
101.
Limiter
AGC
Analog Domain
Section 7.2 “Extended Operating Mode” on
ADC
RSSI
Section 8.6 “Link Quality Indication
parameter 12.5.8. Finally the sig-
RX BBP
Frame
Buffer
Control, Registers
AT86RF231
Digital Domain
33, the reception
SPI
101
SPI
µC
I/F
I/F
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