AT86RF231-ZF Atmel, AT86RF231-ZF Datasheet - Page 122
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AT86RF231-ZF
Manufacturer Part Number
AT86RF231-ZF
Description
TXRX LOW POWER 2.4GHZ 32VQFN
Manufacturer
Atmel
Datasheet
1.AT86RF231-ZUR.pdf
(198 pages)
Specifications of AT86RF231-ZF
Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
Applications
Industrial Monitoring and Control, Wireless Alarm and Security Systems
Power - Output
-17dBm ~ 3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.3mA
Current - Transmitting
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
2405 MHz to 2480 MHz
Interface Type
SPI
Noise Figure
6 dB
Output Power
20 dB
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
12.3 mA
Minimum Operating Temperature
- 40 C
Modulation
OQPSK
Protocol Supported
802.15.4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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9.7.5
9.7.6
8111C–MCU Wireless–09/09
Bit
+0x08
Read/Write
Reset Value
Interrupt Handling
Register Description
CCA_REQUEST
7
W
0
If the PLL operates for a long time on the same channel, e.g. more than 5 min, or the operating
temperature changes significantly, it is recommended to initiate the calibration loops manually.
Both calibration loops can be initiated manually by setting PLL_CF_START = 1 (register 0x1A,
PLL_CF) and register bit PLL_DCU_START = 1 (register 0x1B, PLL_DCU). To start the calibra-
tion the device must be in PLL_ON or RX_ON state. The completion of the center frequency
tuning is indicated by a PLL_LOCK interrupt.
Both calibration loops may be run simultaneously.
Two different interrupts indicate the PLL status (refer to register 0x0F). IRQ_0 (PLL_LOCK) indi-
cates that the PLL has locked. IRQ_1 (PLL_UNLOCK) interrupt indicates an unexpected unlock
condition. A PLL_LOCK interrupt clears any preceding PLL_UNLOCK interrupt automatically
and vice versa.
A PLL_LOCK interrupt is supposed to occur in the following situations:
Any other occurrences of PLL interrupts indicate erroneous behavior and require checking of the
actual device status.
The state transition from BUSY_TX to PLL_ON after successful transmission does not generate
an IRQ_0 (PLL_LOCK) within the settling period.
Register 0x08 (PHY_CC_CCA):
This register sets the IEEE 802.15.4 - 2.4 GHz channel number
• Bit 7 - CCA_REQUEST
Refer to
• Bit [6:5] - CCA_MODE
Refer to
• Bit [4:0] - CHANNEL
The register bits CHANNEL define the RX/TX channel. The channel assignment is according to
IEEE 802.15.4.
• State change from TRX_OFF to PLL_ON / RX_ON / TX_ARET_ON / RX_AACK_ON
• Channel change in states PLL_ON / RX_ON / TX_ARET_ON / RX_AACK_ON
R/W
6
0
CCA_MODE
Section 8.5 “Clear Channel Assessment (CCA)” on page
Section 8.5 “Clear Channel Assessment (CCA)” on page
R/W
5
1
R/W
4
0
R/W
3
1
CHANNEL
R/W
2
0
R/W
1
94.
94.
1
AT86RF231
R/W
0
1
PHY_CC_CCA
122
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