ATMEGA64RZAV-10PU Atmel, ATMEGA64RZAV-10PU Datasheet - Page 11

• Manufacturer Part Number: ATMEGA64RZAV-10PU
• Description: MCU ATMEGA644/AT86RF230 40-DIP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA64RZAV-10PU

• Frequency: 2.4GHz
• Modulation Or Protocol: 802.15.4 Zigbee
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 64kB Flash, 2kB EEPROM, 4kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 40-DIP (0.600", 15.24mm)
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Applications: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega64

Notes:
2593NS–AVR–07/10
0x1B (0x3B)
0x1A (0x3A)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
Address
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these reg-
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O regis-
should never be written.
isters, the value of single bits can be checked by using the SBIS and SBIC instructions.
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
ters as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega644 is a complex
microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and
OUT instructions. For the Extended I/O space from $60 - $FF, only the ST/STS/STD and LD/LDS/LDD instructions can be
used.
PCIFR
Reserved
Reserved
Reserved
TIFR2
TIFR1
TIFR0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PORTD
DDRD
PIND
PORTC
DDRC
PINC
PORTB
DDRB
PINB
PORTA
DDRA
PINA
Name
PORTD7
PORTC7
PORTB7
PORTA7
PIND7
PINC7
PINB7
PINA7
DDD7
DDC7
DDB7
DDA7
Bit 7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTD6
PORTC6
PORTB6
PORTA6
PIND6
PINC6
PINB6
PINA6
DDD6
DDC6
DDB6
DDA6
Bit 6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTD5
PORTC5
PORTB5
PORTA5
PIND5
PINC5
PINB5
PINA5
DDD5
DDC5
DDB5
DDA5
Bit 5
ICF1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTD4
PORTC4
PORTB4
PORTA4
PIND4
PINC4
PINB4
PINA4
DDD4
DDC4
DDB4
DDA4
Bit 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTD3
PORTC3
PORTB3
PORTA3
PCIF3
PIND3
PINC3
PINB3
PINA3
DDD3
DDC3
DDB3
DDA3
Bit 3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PORTD2
PORTC2
PORTB2
PORTA2
OCF2b
OCF1B
OCF0B
PCIF2
PIND2
PINC2
PINB2
PINA2
DDD2
DDC2
DDB2
DDA2
Bit 2
-
-
-
-
-
-
-
-
-
-
-
-
PORTD1
PORTC1
PORTB1
PORTA1
OCF2A
OCF1A
OCF0A
PCIF1
PIND1
PINC1
PINB1
PINA1
DDD1
DDC1
DDB1
DDA1
Bit 1
-
-
-
-
-
-
-
-
-
-
-
-
PORTD0
PORTC0
PORTB0
PORTA0
PIND0
PINC0
PINB0
PINA0
PCIF0
DDD0
DDC0
DDB0
DDA0
Bit 0
TOV2
TOV1
TOV0
ATmega644
-
-
-
-
-
-
-
-
-
-
-
-
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