SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 34

• Manufacturer Part Number: SI4322-A1-FT
• Description: IC RCVR FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: FSK Receiverr

Specifications of SI4322-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1628-5

Si4322
13. Reset modes
The chip will enter into reset mode if any of the following conditions are met:



13.1. Power-On Reset
After power up the supply voltage starts to rise from 0 V. The reset block has an internal ramping voltage reference
(reset-ramp signal), which is rising at 100 mV/ms (typical) rate. The chip remains in reset state while the voltage
difference between the actual V
which is 600 mV (typical). As long as the V
regardless the voltage difference between the V
The reset event can last up to 100 ms supposing that the V
period, the chip does not accept control commands via the serial control interface.
13.2. Power Glitch Reset
The internal reset block has two basic mode of operation: normal and sensitive reset. The default mode is
sensitive, which can be changed by the appropriate control command (see related control commands at the end of
this section). In normal mode the power glitch detection circuit is disabled.
There can be spikes or glitches on the V
the power supply is too high. In such cases if the sensitive reset is enabled an (unwanted) reset will be generated if
the positive going edge of the V
the internal ramp signal and the V
is weak and due to its increased internal resistance a sudden decrease of the current consumption (for example
turning off the power amplifier) might lead to an increase in supply voltage. If for some reason the sensitive reset
cannot be disabled step-by-step decrease of the current consumption (by turning off the different stages one by
one) can help to avoid this problem.
Any negative change in the supply voltage will not cause reset event unless the V
threshold voltage (250 mV in normal mode, 1.6V in sensitive reset mode).
If the sensitive mode is disabled and the power supply turned off the V
trigger a power-on reset event when the supply voltage is turned back on. If the decoupling capacitors keep their
charges for a long time it could happen that no reset will be generated upon power-up because the power glitch
detector circuit is disabled.
Note that the reset event reinitializes the internal registers, so the sensitive mode will be enabled again.
34
Power-on reset: During a power up sequence until the V
Power glitch reset: Transients present on the V
Software reset: Special control command received by the chip
output
nRes
1.6V
V
H
L
dd
DD
DD
DD
has a rising rate greater than 100 mV/ms and the voltage difference between
and the internal reset-ramp signal is higher than the reset threshold voltage,
Figure 7. Power-On Reset Example
reaches the reset threshold voltage (600 mV). Typical case when the battery
DD
Reset threshold voltage
line if the supply filtering is not satisfactory or the internal resistance of
DD
(600 mV)
DD
voltage is less than 1.6 V (typical) the chip stays in reset mode
DD
and the internal ramp signal.
Rev. 1.2
line
It stays in reset because the V
difference is smaller than the reset threshold )
Reset ramp line
dd
DD
(100mV/ms)
has reached the correct level and stabilized
reaches 90% its final value within 1 ms. During this
dd
< 1.6V (even if the voltage
DD
must drop below 250 mV in order to
DD
time
level reaches the reset