SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 20

• Manufacturer Part Number: SI4322-A1-FT
• Description: IC RCVR FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: FSK Receiverr

Specifications of SI4322-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1628-5

Si4322
5.8. Extended Wake-Up Timer Command
These bits can be used to extend the range of the wake-up timer. The explanation of the bits can be found under
the Wake-Up Timer Command description (see above).
5.9. Low Duty Cycle Command
With this command, autonomous low duty cycle operation can be set up in order to decrease the average power
consumption in receive mode.
Bit 7-1 <d6 : d0>: The duty cycle can be calculated by using D <d6 to d0> and M. (M is parameter in a Wake-Up
Bit 0 <enldc>: Enables the low duty cycle mode. Wake-up timer interrupt is not generated in this mode.
Note: For this operating mode, bit en must be cleared in the "5.5. Receiver Setting Command" on page 18 and bit et must be
There is an application proposal shown below. The Si4322 is configured to work in FIFO mode. The chip
periodically wakes up and switches to receiving mode. If valid FSK data received, the chip sends an interrupt to the
microcontroller and continues filling the RX FIFO. After the transmission is over and the FIFO is read out
completely and all other interrupts are cleared, the chip goes back to low power consumption mode.
20
Bit
Bit
set in the "5.3. Configuration Setting Command" on page 16.
In low duty cycle mode the receiver periodically wakes up for a short period of time and checks if there is a valid FSK
transmission is in progress. FSK transmission is detected in the frequency range determined by "5.4. Frequency Setting
Command" on page 18 plus and minus the baseband filter bandwidth set by the "5.3. Configuration Setting Command"
on page 16. This on-time is automatically extended while DQD indicates good received signal condition.
When calculating the on-time take into account the crystal oscillator, the synthesizer, and the PLL need time to start, see
the "Table 2. AC Characteristics" on page 6 depending on the DQD parameter, the chip needs to receive a few valid data
bits before the DQD signal indicates good signal condition "5.12. Data Filter Command" on page
on-cycle can prevent the crystal oscillator from starting or the DQD signal may not go high even when the received sig-
nal has good quality.
Figure 4. Application Proposal for LPDM (Low Power Duty-Cycle Mode) Receivers
15
15
1
1
Transm itter
µC activity
Receiving
Note : Several packets must be transm itted to ensure safe reception
Receiver
nIRQ
DQD
14
14
1
1
Timer Command, see above). The time cycle is determined by the Wake-Up Timer Command.
duty cycle= (D x 2 +1) / M x 100%
13
13
0
0
12
12
0
0
Twake-up
11
11
1
0
10
10
1
0
Packet A
9
0
9
1
Packet A
Packet A
8
0
8
1
FIFO Read
Packet A
d6
c1
Packet A
7
7
Rev. 1.2
, depending on the ratio of the packet length and the idle time between packets
d5
c0 m13 m12 m11 m10 m9 m8
6
6
d4
5
5
Packet
d3
4
4
B. B . B. B.
d2
3
Packet
3
d1
2
B.
2
FF.rd
d0 enldc
1
1
0
0
23.
Choosing too short
CC0Eh
C300h
POR
POR
.