SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 24

• Manufacturer Part Number: SI4322-A1-FT
• Description: IC RCVR FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: FSK Receiverr

Specifications of SI4322-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1628-5

Si4322
Analog RC filter: The demodulator output is fed to pin 7 over a 10 k resistor. The filter cut-off frequency is set by
the external capacitor connected to this pin and VSS.
The table shows the optimal filter capacitor values for different data rates.
Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO cannot be used.
Bit 3 <ewi>:
Bit 2:0 <f2 : f0>: DQD threshold parameter. The Data Quality Detector is a digital processing part of the radio,
If the internally calculated data quality value exceeds the DQD threshold parameter for five consecutive data bits
for both the high and low periods, then the DQD signal goes high.
The DQD parameter in the Data Filter Command should be chosen according to the following rules:



5.13. Data Rate Command
Bit 7 <cs>:
Bit 6:0 <r6 : r0>:
The expected bit rate of the received data stream is determined by the R value and the cs bit. Set R according the
next function:
Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with
small error.
Data rate accuracy requirements:
Clock recovery in slow mode:
BR is the bit rate set in the receiver and
the maximal number of consecutive ones or zeros in the data stream. It is recommended for long data packets to
include enough 1
transmitter.

recovery circuit will always operate below this limit independently from process, temperature, or V
Supposing that the maximum length of consecutive zeros or ones in the data stream is less than 5 bits, the
necessary relative accuracy is 0.68% in slow mode and 2.1% in fast mode.
24
BR is a theoretical limit for the clock recovery circuit. Clock recovery will not work above this limit. The clock
Filter Capacitor Value
The DQD parameter can be calculated with the following formula:
DQD
It should be larger than 4 because otherwise noise might be treated as a valid FSK signal.
The maximum value is 7.
Bit
Data Rate [kbps]
par
15
1
= 4 x (deviation – TX-RX
14
1

Enables the automatic wake-up on any interrupt event. When the ewi bit is set, the crystal
oscillator turns on automatically when an interrupt occurs. This time the crystal oscillator stays
active until all the active interrupts cleared. Clearing the ex bit in the "5.3. Configuration Setting
Command" on page 16 will not stop the oscillator.
connected to the demodulator—it is an indicator reporting the quality of an FSK modulated RF
signal. It works every time when the receiver is on. Setting its parameter defines how clean
should be the incoming data stream to be qualified as good data (valid FSK signal).
0 and 0
Enables the prescaler in the data rate clock generation circuit (1/8 divider)
The seven bit value of R <r6 : r0> sets the divider ratio of the data rate clock generation circuit
13
0
R = (10 MHz / 29 / (1 + cs x 7) / BR) – 1, where BR is the bit rate
12
0

12 nF
1 transitions, and be careful to use the same division ratio in the receiver and in the
1.2

11
1
BR/BR < 1 / (29 x N
offset
10
8.2 nF
0
2.4
) / bit rate

BR is bit rate difference between the transmitter and the receiver. N
9
0
6.8 nF
4.8
8
0
bit
Rev. 1.2
cs
7
)Clock recovery in fast mode:
3.3 nF
9.6
r6
6
r5
5
1.5 nF
19.2
r4
4
r3
680 pF
3
38.4
r2
2

270 pF
r1
BR/BR < 3 / (29 x N
57.6
1
r0
0
150 pF
115.2
DD
C813h
POR
condition.
100 pF
256
bit
)
bit
is