SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 14

• Manufacturer Part Number: SI4322-A1-FT
• Description: IC RCVR FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: FSK Receiverr

Specifications of SI4322-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1628-5

No
No
No
No
Output and FIFO Mode Command
Bit 7-4 <f3 : f0>:
Bit 3-2 <s1 : s0>:
No
No
Not t t t t e e e e e :
Bit 1 <ff>:
Bit 0 <fe>:
No
Not t t t t e e e e e :
No
bit
VDI (Valid Data Indicator) see further details in Receiver Control Word, Synchron word in microcontroller mode is 2DD4h.
To restart the synchron word reception, bit 1 should be cleared and set.
This action will initialize the FIFO and clear its content.
Bit 0 modifies the function of DATA pin and DCLK pin. The DATA pin will become input (nFFS) if fe is set to 1. If the chip is
15
1
14
1
used in FIFO mode, do not allow this to be a floating input.
FIFO IT level. The FIFO generates IT when number of the received data bits reaches this level.
Select the input of the FIFO fill start condition:
Enables FIFO fill after synchron word reception. FIFO fill stops when this bit is cleared.
Enables the 48 bit deep FIFO mode. To clear the counter of the FIFO, it has to be set to zero.
13
0
12
0
CR_LOCK
DQD
VDI
fifo fill enable*
fifo enable*
11
1
10
1
fifo enable*
s1
9
1
0
0
1
1
s0
8
0
0
1
0
1
Sync. Word
DIRECTION
EN
Pad DATA
Detector
I/O Port
nRES
f3
7
Q
Sync. Word
Sync. Word
VDI
SYNC. WORD
logic HIGH
SYNC. WORD
1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2
Always
f2
6
VDI
DATA (from data filter)
CLK (from clock recovery)
NOTE:
* For details see the Output and FIFO Mode Command
s0*
s1*
f1
5
0
1
2
3
M
U
X
f0
4
FIFO WRITE Logic
FIFO_WRITE_EN
nFIFO_RESET
FIFO_WRITE_DATA
FIFO_WRITE_CLK
s1
(simplified)
3
s0
2
1
ff
fe
0
CE87h
POR
Si4322
14