SI4322-A1-FT Silicon Laboratories Inc, SI4322-A1-FT Datasheet - Page 13

• Manufacturer Part Number: SI4322-A1-FT
• Description: IC RCVR FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: FSK Receiverr

Specifications of SI4322-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 256 kbps
• Modulation Or Protocol: FSK
• Applications: Remote Control, RKE, Security Systems
• Current - Receiving: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Frequency: 915 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Current: 12 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 336-1628-5

No
No
Data Filter Command
Bit 7 <al>:
Bit 6 <ml>:
Bit 5 <dsfi>:
Bit 4 <sf>:
Digital: this is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is automatically
adjusted to the bit rate defined by the Data Rate Command.
Analog RC filter: the demodulator output is fed to the DCK pin over a 10 kOhm resistor. The filter characteristic is set by the external
capacitor connected to this pin and VSS. (Suggested value for 9600 bps is 1.8 nF).
Bit 3 <ewi>:
Bit 2-0 <f0:f2>:
No
No
Not t t t t e e e e e :
Data Rate Command
The expected bit rate of the received data stream is determined by the 7-bit value R (bits r6 to r0) and the 1 bit cs.
BR = 10 MHz / 29 / (R+1) / (1 + cs*7)
In the receiver set R according the next function:
R= (10 MHz / 29 /(1 + cs*7)/ BR) – 1
Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error.
Data rate accuracy requirements:
BR is the bit rate set in the receiver and
consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and
be careful to use the same division ratio in the receiver and in the transmitter.
Δ
operate below this limit independently from process, temperature, or Vdd condition.
e.g. Supposing a maximum length of consecutive zeros or ones in the data stream is less than 5 bits, the necessary relative accuracy is
0.68% in slow mode and 2.1% in fast mode.
BR is a theoretical limit for the clock recovery circuit. Clock recovery will not work above this limit. The clock recovery circuit will always
bit
bit
15
15
1
1
To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when the bitrate is close to
the deviation. At higher deviation/bitrate settings higher threshold parameter can report "good signal quality" as well.
Clock recovery in slow mode:
14
14
1
1
Clock recovery (CR) auto lock control if set.
Clock recovery lock control
Disables autosleep on FIFO interrupt if set to 1.
Selects the type of the data filter:
DQD threshold parameter.
It means that the CR start in fast mode after locking it automatically switches to slow mode.
1: fast mode, fast attack and fast release - 0: slow mode, slow attack and slow release
Using the slower one requires more accurate bit timing (see Data Rate Command).
Enables
13
13
0
0
12
12
0
0
the automatic wake-up on any interrupt event.
11
11
0
1
Δ
Δ
10
10
BR/BR < 1/(29*N
BR is bit rate difference between the transmitter and the receiver. N
1
0
9
0
9
0
sf
0
1
8
0
8
0
bit
cs
al
Analog RC filter
7
7
)
Filter Type
Digital
ml
r6
6
6
dsfi
r5
5
5
Clock recovery in fast mode:
r4
sf
4
4
ewi
r3
3
3
f2
r2
2
2
f1
r1
1
1
f0
r0
0
0
Δ
BR/BR < 3/(29*N
bit
is the maximal number of
C462h
C813h
POR
POR
Si4322
bit
)
13