TEF6606T/V5,512 NXP Semiconductors, TEF6606T/V5,512 Datasheet - Page 23

• Manufacturer Part Number: TEF6606T/V5,512
• Description: IC TUNER CAR RADIO AM/FM 32SOIC
• Manufacturer: NXP Semiconductors

Specifications of TEF6606T/V5,512

• Modulation Or Protocol: AM, FM
• Applications: AM/FM Radio Receiver
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 8.5V
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Frequency: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935288263512

NXP Semiconductors
LPC3152_3154
Preliminary data sheet
6.11 DMA controller
USB-IF TestID for Hi-speed peripheral silicon and embedded host silicon: 40720018
The DMA Controller can perform DMA transfers on the AHB bus without using the CPU.
This module has the following features:
Table 10:
[1]
Peripheral name
NAND flash controller/AES decryption engine
SPI
MCI
LCD Interface
UART
I
I
I
PCM interface
2
2
2
•
•
•
•
•
•
•
•
•
C0/1-bus interfaces
S0/1 receive input
S0/1 transmit output
This module has its own, integrated DMA engine.
Supported transfer types:
Memory to memory copy:
– Memory can be copied from the source address to the destination address with a
Memory to peripheral:
– Data is transferred from incrementing memory to a fixed address of a peripheral.
Peripheral to memory:
– Data is transferred from a fixed address of a peripheral to incrementing memory.
Supports single data transfers for all transfer types.
Supports burst transfers for memory to memory transfers. A burst always consists of
multiples of 4 (32 bit) words.
The DMA controller has 12 channels.
Scatter-gather is used to gather data located at different areas of memory. Two
channels are needed per scatter-gather action.
Supports byte, half word and word transfers, and correctly aligns it over the AHB bus.
Compatible with ARM flow control, for single requests, last single requests, terminal
count info, and dma clearing.
Supports swapping in endianess of the transported data.
AES decryption engine is available on LPC3154 only.
specified length, while incrementing the address for both the source and
destination.
The flow is controlled by the peripheral.
The flow is controlled by the peripheral.
Peripherals that support DMA access
All information provided in this document is subject to legal disclaimers.
Rev. 0.12 — 27 May 2010
[1]
Supported Transfer Types
Memory to memory
Memory to peripheral and peripheral to memory
Memory to peripheral and peripheral to memory
Memory to peripheral
Memory to peripheral and peripheral to memory
Memory to peripheral and peripheral to memory
Peripheral to memory
Memory to peripheral
Memory to peripheral and peripheral to memory
LPC3152/3154
© NXP B.V. 2010. All rights reserved.
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