AD6655BCPZ-125 Analog Devices Inc, AD6655BCPZ-125 Datasheet - Page 19

• Manufacturer Part Number: AD6655BCPZ-125
• Description: IC IF RCVR 14BIT 125MSPS 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD6655BCPZ-125

• Function: IF Diversity Receiver
• Frequency: 450MHz
• Rf Type: Cellular, CDMA2000, GSM EDGE, W-CDMA
• Secondary Attributes: 32-Bit Numerically Controlled Oscillator
• Package / Case: 64-VFQFN, CSP Exposed Pad
• Receiving Current: 705mA
• Frequency Range: 450MHz
• Rf Ic Case Style: LFCSP
• No. Of Pins: 64
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Frequency Max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD6655-125EBZ - BOARD EVAL W/AD6655 & SOFTWARE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 12. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
ADC Power Supplies
20, 64
1, 21
24, 57
36, 45, 46
0
ADC Analog
37
38
44
43
39
40
42
41
49
50
ADC Fast Detect Outputs
29
30
31
32
53
54
55
56
Mnemonic
DRGND
DRVDD
DVDD
AVDD
AGND,
Exposed Pad
VIN+A
VIN−A
VIN+B
VIN−B
VREF
SENSE
RBIAS
CML
CLK+
CLK−
FD0A
FD1A
FD2A
FD3A
FD0B
FD1B
FD2B
FD3B
Type
Ground
Supply
Supply
Supply
Ground
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
D13B (MSB)
NOTES
1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
D0A (LSB)
ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
DRVDD
DCOB
DCOA
D10B
D11B
D12B
D6B
D7B
D8B
D9B
D1A
D2A
D3A
D4A
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Figure 9. LFCSP Parallel CMOS Pin Configuration (Top View)
Description
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. The exposed thermal pad on the bottom of the package provides the
analog ground for the part. This pad must be connected to ground for proper operation.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. (See Table 15 for details.)
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Channel A Fast Detect Indicator. (See Table 21 for details.)
Channel A Fast Detect Indicator. (See Table 21 for details.)
Channel A Fast Detect Indicator. (See Table 21 for details.)
Channel A Fast Detect Indicator. (See Table 21 for details.)
Channel B Fast Detect Indicator. (See Table 21 for details.)
Channel B Fast Detect Indicator. (See Table 21 for details.)
Channel B Fast Detect Indicator. (See Table 21 for details.)
Channel B Fast Detect Indicator. (See Table 21 for details.)
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
PARALLEL CMOS
Rev. A | Page 19 of 88
(Not to Scale)
AD6655
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
AD6655