AT86RF211SDK E2V, AT86RF211SDK Datasheet
AT86RF211SDK
Specifications of AT86RF211SDK
AT86RF211-DK915107
AT86RF211DK
AT86RF211DK915107
AT86RF211DK915107
Related parts for AT86RF211SDK
AT86RF211SDK Summary of contents
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Features • Up-compatibility with the AT86RF211 – Same Features as AT86RF211 after Power-on Reset – New Features Activated by a Bit (ADDFEAT) • Shrink Version with a Current Consumption Reduction of 20% • Direct Replacement in Production • Migration Documentation/Kit ...
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FHSS). The AT86RF211S is also well adapted to battery-operated systems can be powered with as little as 2.4V. It also offers a "wake-up" receiver feature ...
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Digital Signal Output DIGOUT 1.1.6 Charge and Hold Data Slicer Mode 1.2 Low-power Standby Modes 1.2.1 PDN Mode 1.2.2 XTAL Running 1.3 Asynchronous Transparent Transmit Mode 5348B–WIRE–03/06 Pin 17 was previously reserved and not connected, but can now deliver ...
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Asynchronous Transparent Receive Mode AT86RF211S 4 Figure 1-1. Asynchronous Transparent Transmit Mode SLE, SCK, SDATA (for set-up) 3 Companion Microcontroller Set up by the MCU in receive mode, the AT86RF211S demodulates any data available on the antenna. The data ...
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Synchronous Receive Modes 5348B–WIRE–03/06 Figure 1-2. Asynchronous Transparent Receive Mode SLE, SCK, SDATA (for set-up) 3 Companion Microcontroller DATAMSG Using a UART controller is a good solution in this case. NRZ or Manchester coding is possible, but is to ...
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Wake-up Mode AT86RF211S 6 Figure 1-3. Synchronous Receive Mode SLE, SCK, SDATA (for set-up) 3 Companion Microcontroller DATAMSG DATACLK The chip is set- special Rx mode called sleep mode. The chip wakes up periodi- cally thanks to ...
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Figure 1-4. Wake-up Overview Step 2: The chip wakes up periodically, waiting for an expected message (stand-alone operation) Step 1: The chip is set-up in sleep mode using the 3-wire interface (SLE, SCK, SDATA), then the microcontroller goes to sleep, ...
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Selecting the Operating Mode Figure 1-6. Flowchart AT86RF211S 8 5348B–WIRE–03/06 ...
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Block Diagram Figure 1-7. AT86RF211S Block Diagram RF FILTER These are the only blocks that depend on the selected ISM band (433, 868 or 915 MHz): dual band applications can be done by only switching them. Synthesizer, loop filter, ...
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Pin Description Table 1-1. Pinout Pin Name Comments 1 RPOWER Full-scale output power resistor 2 TXGND1 GND input/output 4 TXGND2 GND 5 TXGND3 GND 6 TXGND4 GND 7 TXVCC VCC 8 TXGND5 GND 9 DIGND GND ...
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Detailed Description 2.1 Frequency Synthesis 2.1.1 Crystal Reference Oscillator Figure 2-2. Typical Networks XTAL1 ( 6.5/30 pF 5348B–WIRE–03/06 The reference clock is based on a classic Colpitts architecture ...
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Table 2-1. XTO Frequencies Reference Clock Frequency IF1 Frequency 10.245 MHz 10.7 MHz 20.500 MHz (RF211S mode 10.7 MHz only) 20.945 MHz 21.4 MHz 2.1.2 Microcontroller Clocking Capability AT86RF211S 12 Possible IF1 Bandwidth Up to 380 kHz Up to 380 ...
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Figure 2-3. MCU Clocking Capability SLE, SCK, SDATA for Setup MCU Internal Slow Clock 2.1.3 Synthesizer 5348B–WIRE–03/06 AT86RF211S 3 Buffered XTO Output DIGOUT MCU crystal can be spared Refer to “Control Logic” on page 34 for more information. A high-speed, ...
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Receiver Description 2.2.1 Overview and Choice of Intermediate Frequencies 2.2.2 Rx/Tx Switch AT86RF211S 14 Figure 2-5. Choosing the Loop Filter Values Pin 41 FILT1 C1 Data Rate C1 Low 220 pF 2.2 nF Medium 560 pF 5.6 nF High ...
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Image Rejection and RF Filter Figure 2-6. Typical 50Ω SAW Filter Implementation in the 868 MHz Bandwidth SWOUT (pin 48) SPST Switch 2.2.4 First LNA/Mixer 5348B–WIRE–03/06 The immunity of the AT86RF211S can be improved with an external band-pass filter. ...
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IF1 filtering 2.2.6 IF1 Gain and Second Mixer AT86RF211S 16 Figure 2-7. Schematic Input of the LNA RXIN Figure 2-8. Schematic Output of the Mixer The first mixer translates the input RF signal down to 10.7 or 21.4 MHz, ...
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IF1 Narrow Bandwidth Filters 5348B–WIRE–03/06 Figure 2-9. IF1 Filtering IF1OUT (pin 36) 330 Ω Figure 2-10. Schematic Input of the IF1 Amplifier IF1IN IF1DEC Figure 2-11. Schematic Output of the Second Mixer IF1 and IF2 filters can be replaced ...
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IF2 Filtering and Gain 2.2.9 IF2 Amplifier Chain AT86RF211S 18 IF2 filtering provides a narrow channel selection IF2 filter is not used, it should be replaced by a coupling capacitor superior to 1 nF, the IF1 filter ...
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RSSI Output 5348B–WIRE–03/06 Figure 2-13. Input of the IF2 Amplifier IF2IN IF2DEC The RSSI value can be read as a 6-bit word in the Status register. Its value is given in dB and is linear as shown in Figure ...
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Table 2-3. RSSI Clocking Options Bits Mode RSSICLK RF211S only 11 RF211S only 10 RF211S only 01 RF211 or RF211S 00 2.2.11 FSK Demodulator AT86RF211S 20 The RSSI’s dynamic range from a -95 dBm to -45 dBm ...
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Table 2-4. Discriminator Bandwidth Selection Applicable Name Mode RF211 NDB RF211S RF211 SDB RF211S MDB RF211S WDB RF211S Note: Please refer to the Application Note 5348B–WIRE–03/06 Figure 2-16. FSK Demodulator Schematic Fin RBW F D The oscillator’s natural frequency is ...
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Data Slicer 2.2.12.1 External Mode 2.2.12.2 Internal Mode AT86RF211S 22 Hereafter is an example of a possible configuration in the 600 kHz-wide 868 to 868.6 MHz European sub-band, in which the European standard EN 300 220 is applicable: • ...
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Figure 2-18. Data Slicing Parameters Setup Example DISCOUT: Demodulated Data 5348B–WIRE–03/06 Figure 2-17. Data Slicer Schematics DATAMSG + - Choice of internal or external reference for the data slicer To operate this way, one must make sure that the 0 ...
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Charge and Hold Mode Figure 2-19. Charge and Hold Mode Schematics Demodulator Output (DSIN) DAC AT86RF211S 24 After a single charge phase (for example, during a preamble), the comparison threshold of the data slicer is stored in the external ...
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Transmitter Description 2.2.13 Power Amplification Figure 2-21. Output Matching of the Power Amplifier Power Supply Filtering Vcc RF PA Output 5348B–WIRE–03/06 The Power Amplifier has been built to deliver more than 14 dBm ( the three most common ...
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Hardware Control AT86RF211S 26 An Automatic Level Control (ACL) loop is integrated to minimize the PA’s sensitivity to temperature, process and power supply variations. For instance, at 85°C, the output power is approximately 2 dB less than at 25°C. ...
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Software Control 5348B–WIRE–03/06 Table 2-5. Power Levels According to R RPOWER 433 MHz 5.6 kΩ +16 18 kΩ +13 33 kΩ +9 Note: Figures are given for V = 3V, temperature = 25°C, TXLVL = 111, best matching. CC ...
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Digital Features 2.3.1 Clock Recovery Function 2.3.1.1 Preamble 2.3.1.2 Algorithm Overview AT86RF211S 28 The clock recovery algorithm in the AT86RF211S has been improved and the new algo- rithm must be used. To use the new algorithm: 1. Put the ...
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Figure 2-25. Clock Recovery DATAMSG DATACLK 2.3.2 Data Rate Programming 5348B–WIRE–03/06 CLK signal is available as soon as the DATACLK bit is programmed, regardless of the state of the DATAMSG pin. The programmed data rate enables the creation of a ...
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Data Tolerance Programming 2.3.4 Recommended Values Table 2-9. Clock Recovery Recommended Settings Maximum Number of DATATOL Preamble Bytes for Sync 2% 4 bytes of $ recommended 2 bytes of $ byte of $55 Note: 1. ...
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Data Resynchronization Figure 2-27. Benefits of Resynchronization Case No resynchronization DATAMSG DATACLK Center of bit 5348B–WIRE–03/06 Figure 2-26. Clock Recovery Target Position DATAMSG DATACLK First random position of clock's rising edge Target position of clock's rising edge ...
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PLL Lock Detect 2.4 Wake-up Mode 2.4.1 WPER Programming Table 2-11. Wake Up Period Programming WPER[8:0] WPER[8:7] (000) (00 (001) (00 – (00) 10 (07e) (00 (07f) (00 AT86RF211S 32 The ...
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Table 2-11. Wake Up Period Programming WPER[8:0] WPER[8:7] (101) or (081) (10) or (01 (102) or (082) (10) or (01 – (10) or (01) 2 (17e) or (0fe) (10) or (01 ...
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Control Logic 2.5.1 Serial Data Interface 2.5.1.1 Register Interface Format AT86RF211S 34 Table 2-13. WL2 Programming WL2[2:0] Period (000 (001) 1 × WL1 2 (010) 2 × WL1 2 (011) 3 × WL1 2 (100) 4 × ...
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WRITE Mode (R Figure 2-28. Write Chronogram: Complete Write Cycle in a 10-bit Register A[3] A[ Figure 2-29. Write Chronogram: Partial Write Cycle, Writing 2 bits ...
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READ Mode (R Figure 2-30. Read Chronogram: Complete Read Cycle from a 10-bit Register SLE SCK SDATA A[3] A[2 ] SDATA INPUT Direction AT86RF211S 36 The address and R/W bits are clocked on the rising edge of ...
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Figure 2-32. Chronogram with Timing tdle SLE T SCK SDATA A[3] A[2 ] SDATA INPUT Direction 2.5.2 Registers Table 2-14. Register Overview Name Address A[3:0] F0 (0000 (0001 (0010 (0011) 2 CTRL1 (0100) 2 ...
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Table 2-14. Register Overview Name Address A[3:0] - (1101 (1110) 2 CTRL2 (1111) 2 Note: All the registers must be reprogrammed after the voltage supply has been removed, otherwise they will remain in the default state 2.5.2.1 Reset ...
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Name TXLVL TXFS - nbit 14- (000 ) init Register reset value = (10000270 Table 2-16. CTRL1 Detailed Description Number Name of Bits Comments General power-down 0: power down mode; only the serial interface is ...
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Table 2-16. CTRL1 Detailed Description Number Name of Bits Comments Value RSSI hysteresis HRSSI output power selection (000) : minimum transmission level 2 TXLVL 3 (111) : maximum transmission level 2 Tx frequency selection 0: F0 & ...
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While V is being measured possible to measure the DC output of the discriminator Description of RSSI measurement with hysteresis mechanism: if the RSSI measurement is higher than the high RSSI level, DATAMSG is validated ...
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Frequency Registers AT86RF211S 42 . Table 2-19. Overview Name F0, F1, F2, F3 Table 2-20. Detailed Description Number Name of bits Comments Frequency code value default register in TX mode ("0" code in FSK modulation) Frequency ...
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Status Register 5348B–WIRE–03/06 In reception mode, only one frequency needs to be programmed. In transmission mode, two different registers F0 and and F3 must be programmed for 0 code and 1 code transmission. The DATAMSG pin ...
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DTR Register AT86RF211S 44 Table 2-23. Detailed Description Number Name of bits Comments PLL Lock flag 0: PLL unlocked PLLL 1 1: PLL locked Measured RSSI level MRSSI 6 Measured V MOFFSET = 1 MVCC 6 WAKEUP flag Copy ...
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Table 2-26. DTR Overview in RF211S Mode Name XTALRUN SELCH nbit 31-30 29 init 00 0 Name PORTEN PORTPOL nbit 20 19 init 0 0 5348B–WIRE–03/06 Table 2-24. Overview in RF211 Mode Name DSREF[3:0] nbit init The register’s reset value ...
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Name WUSYNC WUHEAD nbit 10 init 0 Table 2-27. DTR Detailed Description in RF211S Mode Number of Name bits XTALRUN 2 SELCH 1 HOLDMODE 1 XTAL205M 1 DISCRANGE 2 DISCLPF 1 RSSICLK 2 – 1 PORTEN 1 AT86RF211S 46 - ...
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Table 2-27. DTR Detailed Description in RF211S Mode (Continued) Number of Name bits PORTPOL 1 PORTSEL 3 CLKOUTPUT 2 NEWDATACLK 1 SYNCDATAMSG 1 DATACLKEN 1 WUSYNC 1 WUHEAD 1 – 3 5348B–WIRE–03/06 Comments DIGOUT pin polarity 0 : low level ...
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Table 2-27. DTR Detailed Description in RF211S Mode (Continued) Number of Name bits DSREF 4 DISCHIGH 1 DISCLOW 1 2.5.2.8 Wake-up Control Register Table 2-28. WUC Overview Name WUE DATA nbit 31 30 init 0 1 Name WL2 nbit 5-3 ...
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Table 2-29. WUC Detailed Description Number Name of bits Comments Wake-up function enable Returns to “0” when a valid message is received. 0: wake-up disable WUE 1 1: wake-up enable Data content 0: message without data field DATA 1 1: ...
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Table 2-29. WUC Detailed Description (Continued) Number Name of bits Comments Minimum delay between TEST 1 and TEST 2 (check of header detection) Variable as multiple of WL1 from × WL1 WL2 3 Inhibit stuff mechanism 0: ...
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Table 2-31. WUR Detailed Description Name Number of bits RATECHK 1 RATE 10 RATETOL 5 2.5.2.10 Wake Up Address Register (WUA) Table 2-32. WUA Overview Name nbit init Table 2-33. WUA Detailed Description Name Number of bits ADDL 5 ADD ...
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Wake-up Data Register (WUD) Table 2-34. WUD Overview Name nbit Table 2-35. WUD Detailed Description Name Number of bits Comments Wake-up message data Warning: the length of this register is variable: WUD Length * case fixed data length (STOP ...
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Table 3-3. Digital CMOS DC Characteristics (unless otherwise specified, data is given for T = 25°C and V Name Parameter CMOS low level input voltage (2) Vil - Normal input (3) - Schmitt trigger input CMOS high level input voltage ...
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Table 3-4. Timings Name Parameter CMOS rise/fall times F SCK frequency T SCK period tw SCK low or high time tsd SDATA setup before SCK rising thd SDATA hold after SCK rising SDATA output propagation delay after ...
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Table 3-5. Synthesizer Specification (unless otherwise specified, data is given for T = 25°C, V Parameter Frequency range Phase noise at 50 kHz Phase noise at 100 kHz Phase noise at 1 MHz Note: 1. iThe crystal frequency can be ...
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Table 3-6. Receiver Specification (unless otherwise specified, data is given for T = 25°C and V Parameter Min Internal switch insertion loss Internal switch isolation Impedance of internal switch 433MHz Impedance of internal switch 868MHz Impedance of internal switch 915MHz ...
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Note: 1. The overall sensitivity depends on the measurement conditions and external components i.e.-102 dBm for BW = ±10 kHz, ∆F = ±7.5 kHz, Brate = 4800 bps with RF switch used and external SAW filter 2. No shielding, 2-layer ...
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Figure 3-2. Typical Supply Current in Rx Mode 28.0 26.0 24.0 22.0 2.25 2.5 Table 3-7. Transmitter Specification (unless otherwise specified, data is given for T = 25°C, V and kΩ) POWER Parameter Output power Output power ...
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Table 3-7. Transmitter Specification (unless otherwise specified, data is given for T = 25°C, V and kΩ) POWER Parameter Range of modulation bandwidth Spurious emissions Spurious emissions Spurious emissions Note: 1. Output power for R = 5.6 ...
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AT86RF211S 60 Figure 3-4. Typical Expected Detailed Current in Tx Mode 434 MHz 25.00 20.00 15.00 10.00 5.00 0.00 2.25 2.50 2.75 3.00 3.25 3.50 Vsupply (V) PA TXVCC EVCC2 EVCC1 CVCC2 CVCC1 RXVCC DIVCC 5348B–WIRE–03/06 ...
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Typical Application 4.1 Implementation Rpower ANTENNA Note: Accurate information regarding the parts and values of the components to be used with the AT86RF211S is described in our Application Note “AT86RF211S FSK ...
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Layout 4.2.1 Reference Design – Top Layer Each unused area must be filled with copper and connected to the bottom side ground plane Decoupling capacitors remain close to the supply pins 4.2.2 Reference Design – Bottom Layer One-block ground ...
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Packaging Information Figure 5-1. 48-lead TQFP Top View Table 5-1. Packaging Description Dimension Nominal Value (mm) A 1.60 A1 0.05 min/0.15 max A2 1.40 D 9.00 D1 7.00 E 9.00 E1 7.00 L 0.60 e ...
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AT86RF211S 64 5348B–WIRE–03/06 ...
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Table of Contents Features ..................................................................................................... 1 Description ................................................................................................ 1 1 General Overview ..................................................................................... 2 2 Detailed Description .............................................................................. 11 3 Electrical Specification .......................................................................... 52 4 Typical Application ................................................................................ 61 5 Packaging Information .......................................................................... 63 6 Ordering Information ............................................................................. 63 Table ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...