4420-DKDB2 Silicon Laboratories Inc, 4420-DKDB2 Datasheet - Page 11

• Manufacturer Part Number: 4420-DKDB2
• Description: KIT DEV TEST EZRADIO SI4420 TRX
• Manufacturer: Silicon Laboratories Inc

Specifications of 4420-DKDB2

• Accessory Type: Test Card, Transceiver, 434MHz
• Wireless Frequency: 434 MHz
• Interface Type: SPI
• Modulation: FSK
• For Use With/related Products: EZRadio®
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CONTROL INTERFACE
Commands (or TX data) to the transceiver are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock
on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of
a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits
having no influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command
registers.
The status information or received data can be read serially over the SDO pin. Bits are shifted out upon the falling edge of CLK signal. When
the nSEL is high, the SDO output is in a high impedance state.
The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:
FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify the
source of the IT, the status bits should be read out.
Timing Specification
Timing Diagram
Symbol
t
t
t
t
t
t
t
t
CH
CL
SS
SH
SHI
DS
DH
OD
 The TX register is ready to receive the next byte (RGIT)
 The FIFO has received the preprogrammed amount of bits (FFIT)
 Power-on reset (POR)
 FIFO overflow (FFOV) / TX register underrun (RGUR)
 Wake-up timer timeout (WKUP)
 Negative pulse on the interrupt input pin nINT (EXT)
 Supply voltage below the preprogrammed value is detected (LBD)
Parameter
Clock high time
Clock low time
Select setup time (nSEL falling edge to SCK rising edge)
Select hold time (SCK falling edge to nSEL rising edge)
Select high time
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
Data delay time
Minimum value [ns]
25
25
10
10
25
5
5
10
Si4420
11