ISA3 Ember, ISA3 Datasheet - Page 96

• Manufacturer Part Number: ISA3
• Description: INSIGHT ADAPTER 3 FOR EM35X
• Manufacturer: Ember

Specifications of ISA3

• Accessory Type: Adapter
• For Use With/related Products: EM35x
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1022

Full TWI frames have to be constructed by software from individual TWI segments. All necessary segment
transitions are shown in Figure 8-2. ACK or NACK generation of a TWI receive frame segment is determined
with the SC_TWIACK bit in the SCx_TWICTRL2 register.
Generation of a 7-bit address is accomplished with one transmit segment. The upper 7 bits of the transmitted
character contain the 7-bit address. The remaining lower bit contains the command type (“read” or “write”).
Generation of a 10-bit address is accomplished with two transmit segments. The upper 5 bits of the first
transmit character must be set to 0x1E. The next 2 bits are for the 2 most significant bits of the 10-bit
address. The remaining lower bit contains the command type (“read” or “write”). The second transmit
segment is for the remaining 8 bits of the 10-bit address.
Transmitted and received characters are accessed through the SCx_DATA register.
To initiate (re)start and stop segments, set the SC_TWISTART or SC_TWISTOP bit in the SCx_TWICTRL1
register, then wait until the bit is clear. Alternatively, the SC_TWICMDFIN bit in the SCx_TWISTAT can be used
for waiting.
To initiate a transmit segment, write the data to the SCx_DATA data register, then set the SC_TWISEND bit in
the SCx_TWICTRL1 register, and finally wait until the bit is clear. Alternatively the SC_TWITXFIN bit in the
SCx_TWISTAT register can be used for waiting.
To initiate a receive segment, set the SC_TWIRECV bit in the SCx_TWICTRL1 register, wait until it is clear, and
then read from the SCx_DATA register. Alternatively, the SC_TWIRXFIN bit in the SCx_TWISTAT register can be
used for waiting. Now the SC_TWIRXNAK bit in the SCx_TWISTAT register indicates if a NACK or ACK was
received from a TWI slave device.
8.5.4
TWI master controller interrupts are generated on the following events:
Bus command (SC_TWISTART/SC_TWISTOP) completed (0 to 1 transition of SC_TWICMDFIN)
Character transmitted and slave device responded with NACK
Interrupts
RECEIVE Segment
STOP Segment
with NACK
Figure 8-2. TWI Segment Transitions
Final
8-21
START Segment
IDLE
NO
TRANSMIT Segment
RECEIVE Segment
received ACK ?
with ACK
YES
EM351 / EM357
120-035X-000G