ISA3 Ember, ISA3 Datasheet - Page 51
![INSIGHT ADAPTER 3 FOR EM35X](/photos/14/2/140217/isa3_sml.jpg)
ISA3
Manufacturer Part Number
ISA3
Description
INSIGHT ADAPTER 3 FOR EM35X
Manufacturer
Ember
Datasheet
1.EM35X-DEV-UPG-IAR.pdf
(245 pages)
Specifications of ISA3
Accessory Type
Adapter
For Use With/related Products
EM35x
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
636-1022
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- Download datasheet (12Mb)
6.5.2
The power management state diagram in Figure 6-3 shows the basic operation of the power management
controller.
In normal operation an application may request one of two low power modes through program execution:
If a deep sleep is requested the EM35x first enters a pre-deep sleep state. This state prevents any section of
the chip from being powered off or reset until the SWJ goes idle (by clearing CSYSPWRUPREQ). This pre-deep
sleep state ensures debug operations are not interrupted.
In the deep sleep state the EM35x waits for a wake up event which will return it to the running state. In
powering up the core logic the ARM
stack and application state to the point where deep sleep was invoked.
Idle Sleep is achieved by executing a WFI instruction while the SLEEPDEEP bit in the Cortex System Control
register (SCS_SCR) is clear. This puts the CPU into an idle state where execution is suspended until an
interrupt occurs. This is indicated by the state at the bottom of the diagram. Power is maintained to the
core logic of the EM35x during the Idle Sleeping state.
Deep sleep is achieved by executing a WFI instruction with the SLEEPDEEP bit in SCS_SCR set. This triggers
the state transitions around the main loop of the diagram, resulting in powering down the EM35x’s core
logic, and leaving only the always-on domain powered. Wake up is triggered when one of the pre-
determined events occurs.
Basic Sleep Modes
Figure 6-3. Power Management State Diagram
®
Cortex
Final
6-13
TM
-M3 is put through a reset cycle and Ember software restores the
EM351 / EM357
120-035X-000G
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