AT86RF211DB-868LT Atmel, AT86RF211DB-868LT Datasheet - Page 5

• Manufacturer Part Number: AT86RF211DB-868LT
• Description: BOARD DAUGHTER AT86RF211/868MHZ
• Manufacturer: Atmel

Specifications of AT86RF211DB-868LT

• Module/board Type: Daughter Board
• For Use With/related Products: AT86RF211 @ 866MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AT86RF211-DB868107; AT86RF211DB868107; AT86RF211DB868107; AT86RF211DB868LT

Practical Implementation
of the Wake-up Mode
How is the Incoming Data
Rate Determined?
Practical Implementation
Data Rates
Mode for the Data Slicer
2186A–WIRE–08/02
The 10 bits Header '1010100001' is a recognition word (that is required to start any
wake-up procedure), also used to extract the data rate value thanks to an embedded
algorithm. In order for this algorithm to operate properly, the duration of the "0" and "1"
must be close one to the other ("duty cycle") within a given tolerance:
•
•
•
Notes:
The following parameters have an influence on the duty cycle:
•
•
•
•
The 2
the PLL). Choosing the loop filter implementation given in chapter 2 ensures that the
duty cycle will NOT be affected by the modulation/demodulation.
The 1
hereafter.
•
•
Atmel recommends:
•
•
Note:
The data slicing is directly acting on the duty cyle of the received '0' and '1'. Two modes
do exist: internal (comparison to a fixed threshold) and external (comparison to the aver-
age value of the signal).
Between 1 kbps and 5 kbps: duty cycle ≤ ± 3%.
Between 5 kbps and 10 kbps: duty cycle ≤ ± 2%.
Between 10 kbps and 20 kbps: duty cycle ≤ ± 1%.
Generation of the sequence by the Tx microcontroller
Modulation of the RF by the Tx RF device.
Demodulation of the received RF signal by the Rx RF device.
Re-shape (data slicing) of the demodulated signal.
The following implementation is simple, and is a very good trade off
simplicity/cost/performances. Atmel highly recommends to follow these
rules.
Should one wants to use another implementation, make sure to contact
Atmel’s FAE before.
a data rate ≤ 10 kbits/s
a generation of the sequence by the Tx microcontroller < ± 1% (very easy to
achieve with a microcontroller)
nd
st
and 4
1. There is no requirement for the data rate accuracy itself (only the "duty cycle" must
2. This requirement only regards the Header (NOT the Address & Data fields)
3. This tolerance has NO relationship with the RATETOL value written into the WUR
4. This Header is set internally and can not be modified by the user
It is possible to use a higher data rate, but it will harden the system requirements and
bring no real advantage. Since it is possible to wake-up a device at 10 kbps and to trans-
fer data at 64 kbps afterwards (see above), and thanks to the wake-up time based on
RSSI checking, the additional power consumption is negligible. Please contact Atmel’s
FAE if application requires a higher data rate during the wake-up phase.
and 3
be within the tolerance).
register, that is used for the rate check feature (see below)
th
rd
points depend on the application and have to meet the rules explained
points depend on the RF component (internal architecture, loop filter of
AT86RF211 (TRX01)
5