CK-S6-SP623-G Xilinx Inc, CK-S6-SP623-G Datasheet - Page 17

• Manufacturer Part Number: CK-S6-SP623-G
• Description: BOARD DEV S6 WITH TX
• Manufacturer: Xilinx Inc
• Series: Spartan™-6r
• Type: FPGAr

Specifications of CK-S6-SP623-G

• Contents: Board, Cables, Documentation, Power Supply
• For Use With/related Products: Spartan™-6 FPGA, XC6SLX150T
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SP623 Board User Guide
UG751 (v1.1) September 15, 2010
200 MHz 2.5V LVDS Oscillator
SuperClock-2 Module
X-Ref Target - Figure 1-7
Table 1-4
Table 1-4: JTAG Isolation Jumpers
[Figure
The SP623 board has one 2.5V LVDS differential 200 MHz oscillator (U7) connected to the
FPGA global clock inputs.
The 200 MHz differential clock is enabled by placing two shunts (P, N) across J188 header
pins 1 – 3 and 2 – 4 (LVDS).
Table 1-5: LVDS Oscillator Global Clock Connections
[Figure
The SuperClock-2 module connects to the clock module interface connector (J32) and
provides a programmable, low-noise clock source for the SP623 board. The clock module
maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock pair, and 1
reset pin.
The SP623 board also supplies VCC5, VCC3V3, VCC2V5, and VCCO input power to the
clock module interface.
Reference Designator
FPGA Pin
1-2, callout 10]
1-2, callout 11]
W24
V23
indicates the FPGA pin name associated with each jumper.
Table 1-6
J195
J196
J22
J23
shows the FPGA I/O mapping for the SuperClock-2 module interface.
FPGA
IO_LVDS_CLK_N
IO_LVDS_CLK_P
U1
Figure 1-7: JTAG Isolation Jumpers
www.xilinx.com
Table 1-5
Net Name
FPGA Pin Name
TDO
TMS
TCK
TDI
TMS
TDO
TCK
TDI
lists the FPGA pin connections to the LVDS oscillator.
J196
J195
J23
J22
U7 Pin
4
5
CFGTCK
CFGTDI
CFGTDO
CFGTMS
System ACE
Controller
UG751_c1_07_050110
U25
Detailed Description
17