CK-S6-SP623-G Xilinx Inc, CK-S6-SP623-G Datasheet
CK-S6-SP623-G
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CK-S6-SP623-G Summary of contents
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SP623 IBERT Getting Started Guide (ISE 12.3) UG752 (v3.0.1) January 26, 2011 ...
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... Revised cover title. Was: “SP623 IBERT Getting Started Guide.” Is: “SP623 IBERT Getting Started Guide (ISE 12.3).” SP623 IBERT Getting Started Guide Revision Connecting the GTP Transceivers and Reference Clocks, 7. Revised Figure 1-1, page 6. Included Si570 initialization instructions in 14. Added ...
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... Appendix A: Running the IBERT Demonstration on Duals 245 and 267 GTP Transceiver Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 GTP TX/RX Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Switch SW3 Setting ...
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SP623 IBERT Getting Started Guide UG752 (v3.0.1) January 26, 2011 ...
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... DC power adapter • CompactFlash memory card containing the IBERT demonstration designs • GTP transceiver power supply module (installed on SP623 board) • SuperClock-2 module (installed on SP623 board) • 12 SMA to SMA cables • One of these JTAG cables: • Platform Cable USB-II (DLC10) • ...
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... The .cpj files are used to load pre-saved MGT/IBERT and clock module control settings for the demonstration. These files must be copied to a working directory on the host computer. To copy the files from the CompactFlash memory card: 1 ...
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... J196 on the SP623 board. 3. Place a jumper across pins 1–2 of the JTAG FMC BYPASS header at J162. 4. Enable the 200 MHz LVDS system clock by placing two jumpers (P, N) across pins 1–3 and pins 2–4 of J188. 5. Verify there MHz oscillator in the SYSTEM ACE CLK oscillator socket at location X1 on the SP623 board ...
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... The SuperClock-2 module provides LVDS clock outputs for the GTP transceiver reference clocks in the IBERT demonstration. SMA connectors on the clock module which can be connected to the GTP transceiver reference clock SMAs on the SP623 board. The four SMA pairs labeled “CLKOUT” provide LVDS clock outputs from the Si5378 clock multiplier/jitter attenuator device on the clock module. The SMA pair labeled “ ...
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... SMA. For example, connect CKOUT1_P (J5) to 101_REFCLK0_P (J59). Note: Any one of the five differential output SMA clocks from the clock module can be used to source either REFCLK0_P|N or REFCLK1_P|N on the SP623 board. Output clocks from the Si5368 device, specifically CKOUT1_P|N and CKOUT2_P|N, are described here and throughout this document as an example ...
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... The final SMA cable connections for Duals 245 and 267 are shown in X-Ref Target - Figure 1-4 Figure 1-4: SMA Cable Connections for Dual 101 and 123 Transceivers and Clocks Configuring the FPGA The following set of instructions describe how to configure the FPGA using the CompactFlash memory card included with the board ...
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To configure from the CompactFlash memory card: 1. Plug the 12V output from the power supply into connector J122. 2. Connect the SP623 board to the host computer. Either of these cables may be used for this connection: • ...
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... Open X-Ref Target - Figure 1-6 Note: IBERT and clock module control parameters. For more information regarding MGT/IBERT settings, refer to UG029, ChipScope Pro Software and Cores User Guide. 12 Configuation Address for Dual 101 and Dual 123 (000) ...
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... Click the Open Cable button X-Ref Target - Figure 1-7 Open Cable Button 4. When the dialog box opens asking to set up the core with settings from the current project, click Yes X-Ref Target - Figure 1-8 5. When the project panel opens, verify the JTAG chain shows the devices listed in ...
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... If using the Si5368 device to source the GTP transceiver clocks (e.g. as described in Table 1-1, page (Figure when the command is complete. X-Ref Target - Figure 1- using the Si570 crystal to source the GTP transceiver clocks, click the Si570 Start button Si570 Done when the command is complete. 14 Figure 1-10: VIO Console Selection 9), initialize the Si5378 device ...
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... X-Ref Target - Figure 1-12 Note: 156.25 MHz. Typing in a different address changes the frequency of the GTP transceiver reference clocks. A complete list of frequency options and their associated ROM addresses is provided the project panel, double-click IBERT Console X-Ref Target - Figure 1-13 Viewing the GTP Transceiver Operation ...
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Running the IBERT Demonstration 1. Note the line rate is 3.125 Gb/s for all four GTP transceivers (MGT Link Status in Figure X-Ref Target - Figure 1-14 Figure 1-14: GTP Transceiver Link Status 16 1-14). www.xilinx.com UG752_c1_17_112310 SP623 IBERT Getting ...
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Note the GTP transmitter differential output swing is preset to 695 mV (0100) as shown in X-Ref Target - Figure 1-15 Figure 1-15: GTP Transceiver TX Differential Output Swing SP623 IBERT Getting Started Guide UG752 (v3.0.1) January 26, 2011 ...
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... Running the IBERT Demonstration 3. Note the RX Bit Error Count as shown in automatically reset to 0.000E000, click the Reset button immediately below the RX Bit Error Count for that particular channel. X-Ref Target - Figure 1-16 Stopping the IBERT Demonstration To stop the IBERT demonstration: 1. Close the ChipScope Pro Analyzer tool. ...
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... Frequency Table Table 2 lists the addresses of the output frequencies of the Si570 and Si5360 programmable clock sources. Table 2: Si570 and Si5368 Frequency Table Address Protocol Frequency 0 Aurora 81.250 1 Aurora 162.500 2 Aurora 325.000 3 Aurora 650.000 4 CPRI 61.440 5 CPRI 122.880 6 CPRI 245.760 7 CPRI 491.520 ...
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Regenerating IBERT Designs Table 2: Si570 and Si5368 Frequency Table (Cont’d) Address Protocol Frequency 90 Generic 340.000 91 Generic 345.000 92 Generic 350.000 93 Generic 355.000 94 Generic 360.000 95 Generic 365.000 96 Generic 370.000 97 Generic 375.000 98 Generic ...
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... SuperClock-2 module through the ChipScope Pro software. The vio_sclk2_control.v module features 84 synchronous inputs (14 free) and 78 synchronous outputs (12 free). No logic exists in this level because vio_sclk2_control.v is only a wrapper. The i2c_sclk2_control module instantiated at this level is a black-box HDL module and is provided as an ISE software v11.4 NGC file. SP623 IBERT Getting Started Guide UG752 (v3 ...
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... Regenerating IBERT Designs CLK50 The IBERT design uses a 25 MHz system clock to match the IBERT requirements. Using the same clock, the I impact on the functionality or performance of the design. Design Notes All files are built using ISE Design Suite, v12.3. The SP623 IBERT design uses a new methodology to combine an IBERT from the CORE Generator software with user logic ...
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... X-Ref Target - Figure 1-17 5. Name the project coregen_top.cgp and click Save “SP623_bot” design, the project will be named coregen_bot.cgp. X-Ref Target - Figure 1-18 SP623 IBERT Getting Started Guide UG752 (v3.0.1) January 26, 2011 Figure 1-17: Open New Project Figure 1-18: Save New Project www ...
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... Regenerating IBERT Designs 6. In the Project Options window, under Part, select the parameters listed here: • Family: Spartan6 • Device: xc6slx150t • Package: fgg676 • Speed Grade: -3 Figure 1-19 X-Ref Target - Figure 1-19 24 shows the correct settings. Figure 1-19: Part Options www ...
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... In the Project Options window, click Generation and select Verilog for Design Entry, select Structural for Preferred Simulation Model, and uncheck the box for ASY Symbol File. Leave the other settings unchanged. settings. X-Ref Target - Figure 1- the Project Options window, under Advanced, leave all settings unchanged. ...
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... Max Rate (Gbps): 3.125 • REFCLK (MHz): 156.25 Note the name for the “SP623_bot” design would be “ibert_s6_bot.” Figure 1-23 After entering the changes to page 1, click Next > to continue to page 2. 26 IBERT Spartan6 GTP (ChipScope Pro - IBERT) 2.01.a Figure Figure 1-22: Select IP Core shows the correct settings ...
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... X-Ref Target - Figure 1-23 12. After page 2 of the IP customization window appears, refer to (check) the tile locations associated with GTP duals 101 and 123 shown in In the GTP1 REFCLK column, refer to associated with the tile location selected in the GUI settings in the GUI should already match the values listed in Note: dedicated reference clock pair associated with the GTP Dual of interest ...
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... Regenerating IBERT Designs X-Ref Target - Figure 1-24 After entering the changes to page 2, click Next > to continue to page 3. 13. Leave page 3 settings as they are. Click Next > to continue to page 4. 28 Figure 1-24: IP Customization, Page 2 Figure 1-25 www.xilinx.com UG752_c1_27_112210 shows the correct settings. ...
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... Frequency (MHz): 25 • Location: $ • Input Standard: LVCMOS25 Figure 1-26 After entering the changes to page 4, Click Next >to continue to page 5. SP623 IBERT Getting Started Guide UG752 (v3.0.1) January 26, 2011 Figure 1-25: IP Customization, Page 3 shows the correct settings. www.xilinx.com Regenerating IBERT Designs ...
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... Regenerating IBERT Designs X-Ref Target - Figure 1-26 15. After page 5 of the IP customization window appears, uncheck the Implement Design box and click Generate 30 Figure 1-26: IP Customization, Page 4 (Figure 1-27). www.xilinx.com UG752_c1_29_112210 SP623 IBERT Getting Started Guide UG752 (v3.0.1) January 26, 2011 ...
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... A readme window for the ibert_s6_top core opens after core generation completes (Figure SP623 IBERT Getting Started Guide UG752 (v3.0.1) January 26, 2011 Figure 1-27: IP Customization, Page 5 1-28). Review the list of files created and click Close when finished. www.xilinx.com Regenerating IBERT Designs UG752_c1_30_112310 31 ...
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... Using a text editor, open the NCF file copied during the previous step and delete the line: NET "IBERT_SYSCLOCK_P_IPAD" LOC = $ | IOSTANDARD = LVCMOS25; 19. The module is now ready to be used in your design (Note: Refer to ibert_s6_top.veo for information on the correct port names for instantiation). ...
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... References UG029, ChipScope Pro Software and Cores User Guide UG751, SP623 Spartan-6 FPGA GTP Transceiver Characterization Board User Guide UG770, HW-CLK-101-SCLK2 SuperClock-2 Module User Guide SP623 IBERT Getting Started Guide UG752 (v3.0.1) January 26, 2011 www.xilinx.com ...
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Warranty Warranty THIS LIMITED WARRANTY applies solely to standard hardware development boards and standard hardware programming cables manufactured behalf of Xilinx (“Development Systems”). Subject to the limitations herein, Xilinx warrants that Development Systems, when delivered by Xilinx ...
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... Substitute the connections for Duals 245 and 267 listed in • Set dip switch SW3 to 001 for Duals 245 and 267 • Run the IBERT demonstration with sp623_bot.cpj GTP Transceiver Clock Connections Table A-1: Duals 245 and 267 Reference Clock Connections Net Name CKOUT1_P CKOUT1_N CKOUT2_P CKOUT2_N ...
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... The final SMA cable connections for Duals 245 and 267 are shown in X-Ref Target - Figure A-1 Figure A-1: SMA Cable Connections for Dual 245 and 267 Transceivers and Clocks Switch SW3 Setting To run the IBERT demonstration on Duals 245 and 267, set the System Ace Controller ...
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... X-Ref Target - Figure A-2 Project Selection Select sp623_bot.cpj and click Open X-Ref Target - Figure A-3 SP623 IBERT Getting Started Guide UG752 (v3.0.1) January 26, 2011 Configuation Address for Dual 245 and Dual 267 (001) On Position = 1 SW3 ADR0 ADR1 ADR2 CFG ADDRESS Figure A-2: DIP Switch SW3 Settings For Duals 245 and 267 ...
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Appendix A: Running the IBERT Demonstration on Duals 245 and 267 38 www.xilinx.com SP623 IBERT Getting Started Guide UG752 (v3.0.1) January 26, 2011 ...