73S1217F-EB-LITE Maxim Integrated Products, 73S1217F-EB-LITE Datasheet - Page 15

• Manufacturer Part Number: 73S1217F-EB-LITE
• Description: BOARD EVAL 73S1217F CBL/DOC/CD
• Manufacturer: Maxim Integrated Products

Specifications of 73S1217F-EB-LITE

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UG_1217F_046
4.2
Rev. 1.2
SERIAL
PORT
232 SHDN
SEL
HEADER 3_0
+5VDC
DB9_RS232
GND
D+
D-
P1
JP2
Schematic
PJ1
J3
USB_CONN_4
VDD
+5VDC
+5VDC
UnReg
5
9
4
8
3
7
2
6
1
GND
GND
GND
VCC
1
2
3
D+
D-
1
2
3
5
4
3
2
1
6
TP1
VDD
VBAT
C20
0.1uF
C21
0.1uF
Length and width of USB D+ and D- tracks
should be matched and routed away from
smart card CLK and VCCs
VBUS
VBUS
VBUS
VBUS
VBUS
VBUS
VBUS
VBUS
VBUS
VBUS
VBUS
VBUS
R25
200k
C29
0.1uF
27
10
12
11
13
14
4
5
6
7
8
9
V+
V-
T1OUT
T2OUT
T3OUT
T4OUT
T5OUT
R1IN
R2IN
R3IN
ENB
SHDNB
R22
VBUS_MON
Enable
R1OUTBF
OSC_IN_32
OSC_IN_32
OSC_IN_32
OSC_IN_32
C10
22pF
C19
0.1uF
R20
R21
100k
R1OUT
R2OUT
R3OUT
T1IN
T2IN
T3IN
T4IN
T5IN
C1+
C2+
C1-
C2-
MAX3237CAI
U3
24
24
28
25
1
3
24
23
22
19
17
16
21
20
18
Y 1
32.768kHz
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DPLUS
DMINUS
JP1
C11
22pF
C22
0.1uF
C23
0.1uF
OSC_OUT_32
OSC_OUT_32
OSC_OUT_32
OSC_OUT_32
R23
200k
Figure 6: 73S1217F Evaluation Board Lite Electrical Schematic
C12
27pF
OSC_IN_12
OSC_IN_12
Install R6, R8, R11 and R12 for Plug
and Play operation, do not install
otherwise
R6
R8
R11
R12
R2
1M
VDD
Y 2
12.000MHz
0
0
0
0
C16
27pF
TP4
TP5
OSC_OUT_12
OSC_OUT_12
USR3
USR2
USR0
USR1
RXD LED
Disable
TXD LED
Disable
VDD
STATUS INDICATOR
RXD
TXD
+
C13
10uF
LED
LED
R5
1
10k
USR0
USR1
USR2
USR3
USR4
USR5
USR6
USR7
RESET
VDD
S1
SW
D5
D6
1000pF
LED0
R18
R19
TP3
1
2
3
4
5
6
7
8
HEADER 8
2
C17
LED
R4
10
USR0
USR1
USR2
USR3
USR4
USR5
USR6
USR7
C33 should be as
close as possible
to pin 65
D1
680
680
VPC
TP7
OSC_OUT_32
OSC_IN_32
OSC_IN_12
OSC_OUT_12
RXD
TXD
TXD
TXD
TXD
TXD
TXD
TXD
TXD
C33
10uF
C14
.1uF
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
U4
1
ON_OFF
VDD
RESET
SEC
ISBR
LED0
SCL
SDA
NC/X32OUT
NC/X32IN
GND
X12IN
X12OUT
COL0
COL1
COL2
ANAIN
COL3
RXD
S2
SW
10uH
VBAT
L1
2
73S1217F
VDD
CLK and Vcc tracks should be
routed away from other Smart
card signals and should be
surrounded by GND.
VCC tracks should be
wider than 0.5mm.
TBUS0
TBUS1
TBUS2
TBUS3
ROW5
ROW4
USR0
SCLK
TCLK
ERST
TEST
RXTX
GND
INT2
INT3
VDD
SIO
C9
4.7uF
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
TP8
1
R1
C9 should
be as close
as possible
to pin 54
INT2
VP
0
USR0
C5 C6 and C7 should be
located close to the
Smart Card Connector
SY M1
Logo
73S1217F Development Board User’s Guide
C5
27p
VDD
Place R'S close to U4
R17
POWER LED
Disable
POWER
HEADER 2 x 4
TP2
R16
C6
27p
R15
62
R14
R24
680
D4
62
LED
R13
JP4
GND
62
R10
R3
100K
62
R9
C24
22pF
62
R7
C30, C31 and C32
should be as
close as possible
to VDD pins on U4
62
C30
0.1uF
62
C25
22pF
C31
0.1uF
62
C26
22pF
VDD
C32
0.1uF
C7
0.47uF
VDD
C27
22pF
VDD
TP6
1
2
C28
22pF
10
1
2
3
4
5
6
7
8
9
Smart Card Connector
J1
VCC
RST
CLK
C4
GND
VPP
I/O
C8
SW-1
SW-2
SMARTCARD
SLOT #1
ISY NC/BRKRQ
VDD
RST_EMUL
TBUS[0]
TBUS[1]
TBUS[2]
TBUS[3]
TBUS[3]
RXTX
TCLK
MOUNT HOLES FOR STAND OFFS
G1 G2 G3 G4
J2
Emulator IF
20
18
16
14
12
10
8
6
4
2
19
17
15
13
11
9
7
5
3
1
15