DK-DEV-4SGX530N Altera, DK-DEV-4SGX530N Datasheet - Page 57

• Manufacturer Part Number: DK-DEV-4SGX530N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IV GXr
• Type: FPGAr

Specifications of DK-DEV-4SGX530N

• Contents: Board, Cable, Documentation, Power Supply
• For Use With/related Products: Stratix® IV GX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2714

Chapter 2: Board Components
Memory
Table 2–46. DDR3 Bottom Port Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
August 2010 Altera Corporation
U5, U12, U18, U24 pin T7
U5, U12, U18, U24 pin T3
U5, U12, U18, U24 pin N7
U5, U12, U18, U24 pin R7
U5, U12, U18, U24 pin L7
U5, U12, U18, U24 pin R3
U5, U12, U18, U24 pin T8
U5, U12, U18, U24 pin R2
U5, U12, U18, U24 pin R8
U5, U12, U18, U24 pin P2
U5, U12, U18, U24 pin P8
U5, U12, U18, U24 pin N2
U5, U12, U18, U24 pin P3
U5, U12, U18, U24 pin P7
U5, U12, U18, U24 pin N3
U5, U12, U18, U24 pin M3
U5, U12, U18, U24 pin M3
U5, U12, U18, U24 pin M3
U5, U12, U18, U24 pin J3
Board Reference
DDR3 Bottom Port
The DDR3 bottom port consists of four DDR3 devices, providing a single 512-Mbyte
interface with a 64-bit data bus. The board supports addressing for up to 4 times the
memory if larger devices become available.
This memory interface is designed to run between 300 MHz, the minimum frequency
for DDR3, and 533 MHz for a maximum theoretical bandwidth of over 68.2 Gbps. The
internal bus in the FPGA is typically 2 or 4 times the width at full-rate or half-rate
respectively. For example, a 533 MHz 64-bit interface will become a 267 MHz 256-bit
bus.
Table 2–46
signal names and types are relative to the Stratix IV device in terms of I/O setting and
direction.
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
Bank address bus
Bank address bus
Bank address bus
Row address select
lists the DDR3 DIMM pin assignments, signal names, and functions. The
Description
Schematic Signal
DDR3BOT_RASn
DDR3BOT_A14
DDR3BOT_A13
DDR3BOT_A12
DDR3BOT_A11
DDR3BOT_A10
DDR3BOT_BA2
DDR3BOT_BA1
DDR3BOT_BA0
DDR3BOT_A9
DDR3BOT_A8
DDR3BOT_A7
DDR3BOT_A6
DDR3BOT_A5
DDR3BOT_A4
DDR3BOT_A3
DDR3BOT_A2
DDR3BOT_A1
DDR3BOT_A0
Name
Stratix IV GX FPGA Development Board Reference Manual
1.5-V SSTL Class I
I/O Standard
Stratix IV GX
Pin Number
Device
AW21
AN14
AK14
AH13
AP15
AG14
AH14
AG15
AK13
AD15
AJ14
AE14
AJ13
AE16
AL15
AF16
AT14
AE15
AF14
2–49