M5373EVB Freescale Semiconductor, M5373EVB Datasheet - Page 28

• Manufacturer Part Number: M5373EVB
• Description: KIT EVAL FOR MCF537X
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: MPUr

Specifications of M5373EVB

• Contents: Module and Misc Hardware
• For Use With/related Products: MCF537x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Characteristics
5.10
The MCF5373 device is compliant with industry standard USB 2.0 specification.
5.11
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
28
1
1
2
3
Num
S11
S12
S13
S14
S15
S16
S17
S18
All timings specified with a capactive load of 25pF.
USB On-The-Go
SSI Timing Specifications
Num
S10
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock
(SYSCLK).
SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the
minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure
that SSI_BCLK does not exceed 4 x f
S1
S2
S3
S4
S5
S6
S7
S8
S9
SSI_BCLK pulse width high/low
SSI_FS input setup before SSI_BCLK
SSI_FS input hold after SSI_BCLK
SSI_BCLK to SSI_TXD/SSI_FS output invalid/high
impedence
SSI_RXD hold after SSI_BCLK
SSI_BCLK cycle time
SSI_BCLK to SSI_TXD/SSI_FS output valid
SSI_RXD setup before SSI_BCLK
SSI_MCLK cycle time
SSI_MCLK pulse width high / low
SSI_BCLK cycle time
SSI_BCLK pulse width
SSI_BCLK to SSI_FS output valid
SSI_BCLK to SSI_FS output invalid
SSI_BCLK to SSI_TXD valid
SSI_BCLK to SSI_TXD invalid / high impedence
SSI_RXD / SSI_FS input setup before SSI_BCLK
SSI_RXD / SSI_FS input hold after SSI_BCLK
MCF537x ColdFire
Description
Table 14. SSI Timing – Master Modes
Description
3
2
Table 15. SSI Timing – Slave Modes
SYS
.
®
Microprocessor Data Sheet, Rev. 4
Symbol
Symbol
t
t
MCLK
t
BCLK
BCLK
1
1
8 × t
8 × t
8 × t
45%
45%
Min
45%
15
—
—
Min
-2
-4
0
10
10
—
-2
3
3
SYS
SYS
SYS
55%
55%
Max
—
—
15
—
15
—
—
Max
55%
—
15
—
—
—
—
—
—
Freescale Semiconductor
Units
t
t
MCLK
BCLK
Units
t
ns
ns
ns
ns
ns
ns
ns
ns
BCLK
ns
ns
ns
ns
ns
ns
ns