M5373EVB Freescale Semiconductor, M5373EVB Datasheet - Page 18

• Manufacturer Part Number: M5373EVB
• Description: KIT EVAL FOR MCF537X
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: MPUr

Specifications of M5373EVB

• Contents: Module and Misc Hardware
• For Use With/related Products: MCF537x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Electrical Characteristics
5.6
Table 9
18
1
2
3
4
5
6
7
8
9
10
11
Num
The maximum allowable input clock frequency when booting with the PLL enabled is 24MHz. For higher input clock
frequencies the processor must boot in LIMP mode to avoid violating the maximum allowable CPU frequency.
All internal registers retain data at 0 Hz.
This parameter is guaranteed by characterization before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This parameter is guaranteed by design rather than 100% tested.
This specification is the PLL lock time only and does not include oscillator start-up time.
C
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the PLL circuitry via PLL V
the Cjitter percentage for a given interval.
Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod.
Modulation percentage applies over an interval of 10 μs, or equivalently the modulation rate is 100 KHz.
14
17
18
19
Modulation range determined by hardware design.
PCB_EXTAL
lists processor bus input timings.
External Interface Timing Characteristics
Discrete load capacitance for EXTAL
CLKOUT Period Jitter,
Frequency Modulation Range Limit
(f
VCO Frequency. f
sys
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter
Max must not be exceeded)
and C
All processor bus timings are synchronous; that is, input setup/hold and output delay with
respect to the rising edge of a reference clock. The reference clock is the FB_CLK output.
All other timing relationships can be derived from these values. Timings listed in
are shown in
PCB_XTAL
vco
Figure 7
Table 8. PLL Electrical Characteristics (continued)
= (f
Characteristic
are the measured PCB stray capacitances on EXTAL and XTAL, respectively.
MCF537x ColdFire
3, 4, 7, 8, 9
ref *
and
PFD)/4
Measured at f
Figure
3, 10, 11
DD
8.
, EV
®
Microprocessor Data Sheet, Rev. 4
DD
SYS
NOTE
, and V
Max
SS
and variation in crystal oscillator frequency increase
C
Symbol
L_EXTAL
C
C
f
vco
jitter
mod
Value
Min.
350
0.8
—
—
C
C
Table 9
PCB_EXTAL
Freescale Semiconductor
S_EXTAL
2*C
Value
Max.
TBD
540
2.2
10
L
–-
–
7
% f
% f
%f
MHz
Unit
pF
sys/3
sys/3
sys/3
sys
.