71M6511H-IGT/F Maxim Integrated Products, 71M6511H-IGT/F Datasheet - Page 61

• Manufacturer Part Number: 71M6511H-IGT/F
• Description: IC ENERGY METER RESIDENT 64-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6511H-IGT/F

• Processor Series: 6511x
• Core: 80515
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 7 KB
• Interface Type: I2C, SSI, UART
• Maximum Clock Frequency: 5 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-64
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: 71M6511H-DB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 22 bit Delta Sigma
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FLSH_ERASE
FLSH_MEEN
FLSH_PGADR
FLSH_PWE
IE_XFER
IE_RTC
INTBITS
LCD_BSTEN
LCD_CLK[1:0]
LCD_EN
LCD_FS[4:0]
Page: 61 of 98
A Maxim Integrated Products Brand
SFR 94
SFR B2[1]
SFR B7[7:1]
SFR B2[0]
SFR E8[0]
SFR E8[1]
SFR F8[6:0]
2020[7]
2021[1:0]
2021[5]
2022[4:0]
© 2005–2010 Teridian Semiconductor Corporation
W
W
W
R/W
R/W
R
R/W
R/W
R/W
R/W
This bit is automatically reset after each byte written to flash. Writes to
this bit are inhibited when interrupts are enabled.
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or
the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle.
(default = 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write
Any other pattern written to FLSH_ERASE will have no effect.
Mass Erase Enable
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Flash Page Erase Address
FLSH_PGADR[6:0] – Flash Page Address (page 0 thru 127) that will be
erased during the Page Erase cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.
Program Write Enable
0 – MOVX commands refer to XRAM Space, normal operation
1 – MOVX @DPTR,A moves A to Program Space (flash) @ DPTR.
Interrupt flags. These flags are part of the WDI SFR register and mo-
nitor the XFER_BUSY interrupt and the RTC_1SEC interrupt. The
flags are set by hardware and must be cleared by the interrupt handler.
See also WD_RST.
Interrupt inputs. The MPU may read these bits to see the input to
external interrupts INT0, INT1, up to INT6. These bits do not have any
memory and are primarily intended for debug use.
Enables the LCD voltage boost circuit.
Sets the LCD clock frequency for COM/SEG pins (not the frame rate.
Note: f
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are
ground as are the COM and SEG outputs.
Controls the LCD full scale voltage, VLC2:
VLC
2
w
=
= CKFIR/128
to FLSH_PGADR @ SFR 0xB7.
to FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must
be enabled.
00: f
VLCD
w
/2
⋅
9
0 (
Single-Phase Energy Meter IC
, 01: f
(default).
7 .
+
0
w
/2
3 .
71M6511/71M6511H
8
LCD
, 10: f
31
DATA SHEET
_
w
FS
/2
7
, 11: f
)
w
/2
6
NOVEMBER 2010
V2.7